1 Introduction↩︎

Internet of Things (IoT) plays a vital role in shaping the modern world [1]. With rapid advancements in Artificial Intelligence (AI), the implementation of complex IoT architectures has become significantly more accessible and efficient. Robotics, in particular, integrates seamlessly with the IoT ecosystem, enabling the deployment of autonomous systems across smart healthcare, intelligent cities, and industrial automation. Autonomous drones, for example, are increasingly being deployed in diverse domains ranging from large-scale public events to military operations [2]. Furthermore, Large Language Models (LLMs) accelerate IoT development by assisting with code generation, system design, and predictive analytics, making these technologies more accessible to developers across varying expertise levels. Recent market forecasts estimate that approximately 9.1 billion active autonomous "smart" devices (AIoT) will be active worldwide by 2033. This exponential growth is anticipated to accelerate the transition toward Industry 5.0, emphasizing human-centric manufacturing, sustainability, and resilience through the integration of advanced digital technologies [3].

The rapid proliferation of AI-enabled IoT systems also expands the attack surface, thereby increasing system vulnerabilities. Recent studies have demonstrated that advanced AI agents can identify and exploit software weaknesses with increasing sophistication [4]. Even with protective guardrails in place, many users actively attempt to jailbreak and test AI models to identify exploitable security gaps. To address these integration challenges, Anthropic developed an open-source protocol called the Model Context Protocol (MCP) designed to safely connect external tools, applications, and data sources to AI models. However, there have been numerous cases of AI agents being misused, leading to unauthorized access, security breaches, and cyberattacks [5].

The rapid development in AI, and IoT devices has been made possible only with the shrinking transisor size on a chip [1]. Requirement for very high performance and ultra low power devices has never been so high. In recent years, AI has driven the demand for high-performance computing chips, including those equipped with high-bandwidth memory. The memory bandwidth for Nvidia H200 chips is 4.8 TB/s [6] which has risen from 336.5 GB/s on its Nvidia Titan X graphics processing units (GPUs) in 2015. Fin Field-Effect Transistors (FinFETs), 3D transistors that employ fin-shaped channel structures, has enabled to continue miniaturizing transistor dimensions to advanced technology nodes. Scaling bulk CMOS or planar transistors has been challenging beyond 32nm. But scaling resumed beyond 22nm with the FinFETs architecture and geometry. These advancements have enabled the development of high-performance, ultra-low-power devices for embedded and IoT applications.

Fig. 1 illustrates the architecture of wearable devices within the broader IoT ecosystem. Recent advances in consumer-grade Large Language Models (LLMs) have further simplified the development of wearable IoT applications by assisting with software development, system integration, and intelligent data processing. There are many commercial wearable headsets which are used in various applications, including opticians to diagnose various issues [7], [8]. There are also many other applications of wearable devices in Smart Healthcare [9] as shown in Fig. 1.

This paper presents a PUF architecture that can be used to secure the resource-constrained wearable technologies. Many vulnerabilities and security concerns were identified in the software and hardware developed using LLMs. Georgia Institute of Technology researchers recently released an article showing the risks of developing the software and hardware using AI models [10]. Google Threat Intelligence Group (GTIG) recently published an article showing the first known threat actor using a zero-day exploit believed to have been developed with AI [11]. The vulnerability allowed bypassing two-factor authentication after valid credentials were obtained and that it was a semantic logic flaw involving incorrect developer assumptions. Currently, AI primarily enhances the capabilities of human attackers rather than replacing them. It accelerates research, software development, reconnaissance, phishing campaigns, and exploit development. [11]. In this context, PUFs provide a hardware-assisted security primitive capable of generating device-unique cryptographic keys and strengthening hardware-rooted trust, thereby helping to mitigate several classes of attacks against resource-constrained IoT systems.

This paper is organized as follows: Section 2 presents the state of the art of Hardware Assisted Security while the novel contributions of the paper are presented in Section 3. An introduction to PUF, its working and applications are presented in Section 4. The architectures of PUF are presented in Section 6. Section 7 presents the simulation results and the conclusion and the future directions of this research is presented in Section 8.

2 Security of Wearable Devices - Challenges and Hardware-Assisted Security (HAS) Approach as a Solution↩︎

Wearable devices have become increasingly prevalent in recent years [12]. The global adoption of smartwatches and other wearable technologies continues to grow annually, driven by advances in sensing, connectivity, and artificial intelligence. These devices continuously collect physiological and environmental data, which are typically transmitted to cloud platforms for storage, analysis, and remote access. Wearable technologies have found widespread applications in both civilian and military domains, including health monitoring, fitness tracking, remote patient care, situational awareness, and mission-critical operations.

2.1 Security Challenges of Wearable Devices↩︎

Wearable devices offer numerous benefits that enhance consumers’ quality of life. Fitness tracking is one of the key features that has contributed to the growing popularity of wearable technologies in the consumer market [9]. Researchers around the world are using the wearable devices for developing IoT architectures for applications such as sleep monitoring, thyroid monitoring [13] and other healthcare services. They constantly gather user information and transmit to the cloud. In certain applications, healthcare providers can remotely monitor patient data, enabling improved access to medical services and real-time health assessment [9].

Despite these advantages, wearable devices introduce security and privacy vulnerabilities that may expose sensitive user information to unauthorized entities [14]. Several commercial wearable devices have faced restrictions or bans in certain workplaces due to privacy concerns. For example, smart glasses can potentially record images or videos without the awareness or consent of individuals, creating risks in sensitive workplace environments. Additionally, wearable devices may collect personal information, including heart rate, location, and sleep patterns, when users enable such data-sharing features. Unauthorized access to this information could reveal sensitive details about users’ health, daily activities, and lifestyles. Fig. 2 illustrates the major security challenges associated with wearable devices.

There are many security vulnerabilities that affect wearable devices as shown in the figure [15]–[17]. An attacker can get information from the devices using side channel attacks [18]. These attacks take advantage of the vulnerabilities in the hardware rather than in the software. Attackers can exploit devices through side-channel attacks by analyzing power consumption, signal timing, and, in some cases, sound. Attackers also introduce Trojans into the devices and eavesdrop into the conversation in the network.

2.2 Hardware-Assisted Security (HAS) - Brief Introduction↩︎

Hardware-Assisted Security (HAS) is a promising approach for addressing these security challenges. A HAS is an extra module dedicated for security in the system. Numerous HAS solutions have been proposed for IoT applications, offering various levels of security capabilities. Some HAS modules can perform end-to-end encryption of the communication channel, while others do not have this capability [19]. The functionality and design of a HAS module depend on the specific application requirements, system constraints, and security specifications.

One of the widely used HAS is Trusted Platform Module (TPM). It is an add-on module that has wide range of applications, from personal computers and servers to small IoT devices [14], [20]. A TPM is a multifunction module that can perform tasks like encryption, decryption, and other cryptographic operations like hashing. TPM can also produce random numbers for keys and in some cases like RSA generate public and private key pairs. One disadvantage is that unlike a PUF, a TPM produces pseudorandom numbers using a program to generate the random numbers.

Another commonly used HAS module is ARM Trustzone [21]. This is a commercially available solution by ARM that is similar to a TPM but also provides a quarantine zone for performing the cryptographic tasks [22]. Arm Trustzone has the ability to generate keys, perform encryption and decryption and provide hashing algorithms similar to a TPM. Arm also uses hardware based key generation similar to the PUF. However, one disadvantaeg of ARM TrustZone is that it is more expensive compared to a TPM.

The third widely used HAS module is PUF [23]. It can generate keys necessary for end-to-end encryption of communication channel, device identification and authentication in a network. They have several other applications as well. PUFs exploit naturally occuring nanoscale manufacturing variations to generate keys; therefore, the resulting keys are inherently random adding an extra layer of security to the overall system. [24]. Attackers cannot identify the keys generated by PUF module. A PUF on its own cannot perform cryptographic tasks, such as encryption and decryption, but when integrated with a cryptoprocessor, it can provide better security.

2.3 Hardware-Assisted Security (HAS) is Best Suitable for Wearable Devices↩︎

Wearable smart devices are embedded systems that run on batteries. These devices continuously monitor the user information and transmit to the cloud or store it locally for later access. This introduces privacy and security risks as discussed earlier. A misplaced wearable device, with a weak password can potentially put the user privacy at risk.

Many software-based security solutions require high processing power or utilize significant device resources. Wearable devices have limited resources and must operate in a resource-constrained environment. Hence, adding an extra HAS module can help in the case of a wearable device. All the cryptographic processes will be off-loaded to the HAS which reduces the load on the main embedded processor.

A PUF module has the ability to generate multiple keys. With an appropriate PUF integrated into the design, it can generate multiple keys, potentially thousands in some architectures. This can be very helpful when the system is under attack. Although a PUF can generate a large number of keys, not all of them can be used for cryptographic purposes. Even when the system is under attack, the keys can be changed on-the-fly if necessary.

3 Novel Contributions↩︎

3.1 Problem Definition↩︎

Previous sections discussed various security vulnerabilities associated with wearable devices. There are many vulnerabilities that an attacker can utilize and gain access to the system [15]–[17]. The “things” in the IoT network are low-power resource-constrained devices that cannot execute resource-intensive cryptographic algorithms. Furthermore, the limited storage capacity of these devices makes it challenging to securely store long cryptographic keys required for end-to-end encryption. A device key, once compromised, can potentially provide access to the entire IoT ecosystem.

3.2 Proposed Solution↩︎

HAS is one of the potential solutions for IoT and wearable devices. PUF modules help achieve robust security in IoT environments. Keys generated by a PUF module cannot be reproduced in any other module. Even if the attacker gets hold of the key, it can be changed on-the-fly using an appropriate PUF architecture.

This paper analyzes two designs of PUF architectures, Arbiter and Hybrid Oscillator Arbiter (HOA) PUF. These two PUF Architectures were selected for IoT security because they exhibit a very low key generation error rate. The key size can be scaled according to the available resources, and the proposed designs are reconfigurable. This paper presents the PUF architectures, their simulation results and an analysis demonstrating their sustainability for tailored IoT architectures.

4 State Of The Art Of Physical Unclonable Function↩︎

During the fabrication of an Integrated Circuit (IC), several manufacturing variations get introduced that are uncontrollable, unavoidable, unpredictable and naturally occurring. Although technology has advanced sufficiently to manufacture ultra low power devices at very small technology nodes, the manufacturing variations have been affecting the yield of the final chips for decades [25]. Moreover, they not only degrade device performance but also influence aging effects throughout the device’s operational lifetime [26].

PUF uses these manufacturing variations to generate the random numbers [27]. These random numbers generated by the PUF are used for a wide range of cryptographic applications, including smart healthcare, smart agriculture, smart cities, and other IoT applications [28], [29]. Fig. 3 shows the working of a PUF. Consider two PUF modules, \(P_1\) and \(P_2\). The input to a PUF is called a “challenge" and the random number output generated from the PUF module is called”response”. Given a PUF module \(P_1\), a challenge produces a corresponding response and these two are called “challenge reponse pair” (CRP) for that module. Every new challenge of PUF must produce a new response. If “N” challenges are given to a PUF, it generates “N” responses.

PUFs have numerous cryptographic applications, including device authentication, encryption, blockchain, and particularly in mission-critical domains such as healthcare, defense, and military systems. To employ PUF modules in cryptographic applications, the PUF modules must satisfy Figures of Merit (FoM) which are discussed further in section 7.

PUFs are classified into various architectures based on their underlying core components. These architectures include SRAM PUFs, Ring Oscillator (RO) PUFs, Quantum PUFs, and other variants. [27], [30], [31]. PUFs are classified into four categories based on the number of keys each architecture can generate while satisfying the required FoMs [32] as shown in Fig. 4:

• Weak PUF

• Strong PUF

• Reconfigurable PUF

• Public PUF

4.1 Weak PUF↩︎

Weak PUFs can generate only a limited number of random numbers that satisfy the Figures of Merit (FoMs). In certain cases, the number can be as low as ‘1’. The number of keys generated that can satisfy the FoMs depends on the manufacturing variations present in the IC. One such architecture that generates limited number of reliable cryptographic keys is SRAM PUF [33]. One limitation of SRAM PUF that results in a low number of usable keys is the occurrence of errors during key generation. Various factors, such as temperature, voltage fluctuations, and humidity, affect its performance, necessitating the use of fuzzy extractors. Although it is a weak PUF, almost every IoT device or board has an SRAM module, making its implementation relatively easier.

4.2 Strong PUF↩︎

Some PUF architectures, such as Arbiter PUF, can generate a larger number of cryptographic keys that satisfy the FoMs. These are called "Strong PUFs" [23]. This increases the robustness of the PUF and expands its range of applications. In certain cases, the number of usable keys can reach several hundreds. Unlike SRAM PUF, most of these architectures are application-specific modules requiring additional hardware on the chip, resulting in trade-offs between battery life and performance. Recent developments in quantum technology have also led to the emergence of quantum PUF architectures.

4.3 Reconfigurable PUF↩︎

Architectures such as Arbiter PUFs remain vulnerable to machine learning attacks [27]. With the rapid growth of AI, even the natural randomness introduced in PUF modules is susceptible to modeling attacks. To resist such adversaries, PUFs can be reconfigured on-the-fly to generate multiple responses. This capability proves particularly valuable in applications requiring a high volume of keys, such as networking.

4.4 Public PUF↩︎

A public PUF differs fundamentally from the traditional PUF. Unlike Strong or Weak PUFs, where the challenge-response behavior must remain confidential to preserve security, a Public PUF is characterized by having a publicly available mathematical model that can simulate its behavior. However, the critical distinguishing feature is that while this model can accurately predict the PUF’s responses, doing so requires significantly more computational time and resources than physically querying the actual device itself. This asymmetry between the ease of physical measurement and the computational difficulty of simulation forms the security foundation of Public PUFs. This property enables unique cryptographic protocols, such as certificate-based authentication and secure key exchange [32].

4.5 Other PUF Classifications↩︎

The classification mentioned above is based on the number of CRPs generated that can satisfy the FoMs. PUF is classified into two categories based on the material used to design the PUF. They are Silicon PUFs and Non Silicon PUFs.

Silicon PUFs are the most widely studied and implemented category, leveraging inherent manufacturing variations present in silicon-based semiconductor devices such as transistors, gate delays, and memory cells. These variations arise naturally during the CMOS fabrication process due to microscopic differences in doping concentrations, oxide thickness, and threshold voltages, even when devices are manufactured using identical masks and processes. The Arbiter PUF, SRAM PUF, and Ring Oscillator (RO) PUF architectures discussed in the previous subsections are examples of silicon-based PUFs. [24], [33], [34].

Non-Silicon PUFs, on the other hand, derive their unique responses from physical phenomena outside conventional silicon-based transistor structures. These architectures exploit properties such as optical scattering, magnetic characteristics, or intrinsic material variations to generate unclonable identifiers. One such architecture is the Optical PUFs, which utilizes the unique scattering patterns produced when light passes through randomly structured optical media [35]. The other type of Non-Silicon PUFs is the Magnetic PUFs, which rely on the unpredictable magnetic domain patterns in materials [36]. With the advancements in Quantum technology, quantum-based PUFs have also been introduced for post-quantum cryptographic applications [30].

5 Related Prior Research↩︎

With the rapid advancement of AI, the demand for high performance and high throughput devices has increased significantly. In particular, the memory bandwidth of the GPU has increased by more than tenfold over the past decade [6], [41]. There are several challenges associated with implementing AI at the scale required [42]. Among these, the power consumption and the performance of the transistor devices are the two most significant challenges. In particular, research on transistor devices focuses on device scaling with an intent to maximize density, high throughput and ultra-low power consumption.

Technology scaling has reached the atomic level [43]. Technology scaling has reached a level that has never been seen before. Such atomic scaling levels were not possible with the planar transistors. Bulk CMOS transistors could scale well until the 32nm technology node. However, the one dimensional planar CMOS transistor geometry was not sufficient for scaling beyond 32 nm into the 22nm. Consequently, 3-dimensional FinFETs were developed to overcome this scaling challenge of conventional planar transistors [44], [45]. Due to this increase in transistor density on a single die, high performance SoCs and NoCs have become feasible which accelerated growth and widespread development of IoT.

The price of the final chip is decided based on the yield [1]. The yield in particular is affected by the manufacturing variations introduced during the fabrication of the IC. As mentioned in previous section, they are naturally occurring, unavoidable, unpredictable and uncontrollable. Hence the research community started using the naturally introduced variations for cryptographic purposes. These are used for generating the natural random numbers using the PUF modules.

With the availability of high performance and low power technology nodes, researchers around the world have started developing IoT architectures for a wide range of applications, including smart healthcare, wearable technologies, and smart transportation over the last few decades. For example, a quadrature design using only standard components was developed in 2016 by Kougianos et al. for real-time object tracking [46]. A thyroid monitoring system was proposed by Prabha et al. in 2016 [13] as an application of smart healthcare. Recently, commercial wearable virtual reality (VR) headsets have become widely available, demonstrating the rapid evolution and growing maturity of wearable technologies [7]. The availability of highly capable commercial AI platforms, such as OpenAI, Google Gemini, and Anthropic’s language models, has simplified software development by assisting with code generation, debugging, documentation, and system integration [47]–[49].

Widespread adoption of AI models has increased cybersecurity challenges [4]. Commercially available AI models have brought to light several unknown software vulnerabilities, including zero-day vulnerabilities [50]. Furthermore, large language models (LLMs) and agentic AI systems have increasingly been used to discover security flaws in commercial and enterprise-grade software and hardware [51]. A single solution might not be able to resist these attacks, but one of the solutions is to use Hardware Assisted Security (HAS). PUF is one such HAS primitive that can generate true random numbers using manufacturing variations. Research based on PUF has been conducted extensively over the last few decades. In [52], a ring oscillator-based PUF (RO PUF) was developed. In [53], a trusted sensor for mobile applications was proposed. Furthermore, in [54] a PUF was presented that is tolerant to process variations, temperature changes, and voltage fluctuations.

This paper mainly discusses two architectures of PUF: RO PUF and Arbiter PUF [55], [56]. These PUF architectures have been evaluated and implemented in many applications. Several other PUF architectures have also been proposed, including SRAM PUFs [57], which have been studied since the early development of PUF-based security solutions. One advantage of SRAM PUF is that most IoT devices already contain embedded SRAM, which can potentially be used to generate keys using PUF. However, SRAM PUFs are susceptible to environmental variations and noise during key reconstruction, necessitating the use of additional error correction mechanisms, such as fuzzy extractors, to reliably generate cryptographic keys.

An Oscillator Collapse Physical Unclonable Function (OC-PUF) was proposed by Zayed et al. in [58]. The architecture proposed in the paper is focused mainly on the power consumption that is more suitable for devices with resource constraints. The authors used a 20nm trigate FinFET architecture for the simulation. The overall power consumption of the device is about 140 nW with the worst case simulations showing a 750 nW power consumption. The reliability of the proposed design is 99 % with a uniqueness of 50.01 %.

A Hybrid Ring Oscillator Arbiter PUF is proposed by Driemeyer et al. in [59]. The authors utilized a 28nm planar CMOS technology to simulate and evaluate the proposed design. The primary objective of this architecture is to develop a high-speed PUF capable of generating cryptographic keys at a high bit rate while maintaining low power consumption. The PUF architecture in [59] generates the keys at a rate of 4.515 Gbits/sec while consuming about 0.259 pJ/bit.

Pahlevi et al. proposed a Per-Selection-Enhanced Arbiter PUF architecture in [60]. The authors evaluated the proposed design using 56 FPGA boards to assess its performance and reliability. The primary focus of the architecture presented in [60] was improving the authentication performance, particularly in terms of the False Acceptance Rate (FAR) and the False Rejection Rate (FRR), which remained below or close to 2.5.

Das et al. proposed a PUF architecture based on voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) in [61]. The proposed PUF architecture achieves a uniqueness of 50.2% and a reliability of 97.3%. Furthermore, the architecture demonstrates strong resistance against machine learning (ML)-based modeling attacks. For example, a multilayer perceptron (MLP) attack achieved a prediction accuracy of less than 55.27%, indicating improved resilience against ML-based attacks. The proposed PUF consumes approximately 63.67 fJ/bit while generating cryptographic keys at a bit rate of 0.27 Gb/s.

6 PUF Architectures of Energy-Efficient Low-Overhead Wearable Security↩︎

This section presents the HOA-PUF architecture for energy-efficient low-overhead wearable security. The core components of the HOA-PUF are Ring Oscillator (RO) PUF and the Arbiter PUF. Both of these architectures have been extensively studied over the years and have demonstrated reliable performance. These PUF architectures can be implemented on an FPGA without requiring fabrication, making them suitable for rapid prototyping and performance evaluation in low-power applications, such as the Internet of Things (IoT). This provides researchers with the advantage of readily integrating the same module into IoT environments for rapid prototyping, testing, and deployment.

6.1 Ring Oscillator PUF↩︎

The architecture of RO PUF is shown in Fig. 6. The inverter is the fundamental building block of an RO PUF. As illustrated in the figure, the architecture consists of two sets of ROs connected to multiplexers. The challenge inputs are applied as select lines to the multiplexers. When a challenge is applied to the PUF, one RO is selected from each set and the resulting oscillation signals are passed to the counters. These counters measure the frequencies of the selected ROs. Finally, a comparator evaluates the frequency difference between the selected ROs and generates the output response bit as either ‘1’ or ‘0’.

The inverter, as the fundamental component of an RO PUF, captures inherent manufacturing variations, including gate delays, dopant concentration variations, and temperature-induced parameter shifts, which influence the final key generation process. Although all ring oscillators are designed identically with the same number of stages, process variations during fabrication introduce subtle, yet significant, differences in signal propagation delays. These variations contribute to the unique physical characteristics of each device and enable the generation of device-specific random responses.

6.2 Design of Arbiter PUF↩︎

Fig.7 illustrates the architecture of the Arbiter PUF consisting of two series of multiplexers. The output of the multiplexers in the first stage is connected to the input of the multiplexers in the subsequent stage. The challenge given to the PUF feeds the select lines of the multiplexers. The outputs of the multiplexers in the final stage are connected to a D flip-flop, with one output connected to the D input and the other connected to the clock input of the flip-flop. The flip-flop determines the final response bit based on the relative delay difference between the two paths.

The core component of an Arbiter PUF is the multiplexer. These multiplexers capture manufacturing variations and subtle differences in transistor geometries introduced during the fabrication process. The propagation delay introduced by each multiplexer stage accumulates through the delay paths, ultimately affecting the timing relationship between the two signals arriving at the D flip-flop. An input is applied simultaneously at the first stage of both series of multiplexers. The path this input takes through both the series of Multiplexers differs based on the challenge given to the PUF. Due to the gate delay added by each transistor and other components, the signals reach the D-flipflop at different times. If the signal connected to the D input arrives before the clock signal, the PUF generates an output response of ‘1’. Conversely, if the clock signal arrives before the D-input signal, the output response is ‘0’. The Arbiter PUF architecture shown in Fig.7 generates a 1-bit response for each applied challenge. Multiple Arbiter PUF instances can be combined to increase the output bit length of the overall PUF module.

6.3 Inverter-based HOA-PUF↩︎

Fig. 8 shows the design of HOA PUF. The core component of the design is the inverter as shown in the figure. Similar to the arbiter PUF, the delay is introduced to the signal by the inverters.

There are two sets of ROs in the design. All ROs in group 1 are connected to multiplexer 1 (MUX 1), while ROs in group 2 are connected to MUX 2. The architecture and design parameters of the ROs in both groups are identical. However, during the fabrication process, there are unforeseen manufacturing variations in which the output frequencies of individual ROs are not identical. As a result, each RO exhibits a unique oscillation frequency, which contributes to the generation of the PUF response. A D-flip-flop is used as the arbiter in the final stage of the circuit. The output of MUX 1 is connected to the D input of the flip-flop, while the output of MUX 2 is connected to the clock input. The challenge given to the PUF is fed as the select signal to these multiplexers. Unlike Arbiter PUF, this design has multiplexers and requires only one D-Flipflop.

The challenge decides the ROs that are selected for the output bit. A pair of ROs will generate one output bit similar to the RO PUF. The number of RO pairs selected decides the length of the output key. The length of the key varies with the design and the number of RO stages used in the architecture. Although there can be an exponential number of combinations of ROs, which gives a huge number of keys, not all of them can be used for applications. FoMs must be satisfied before they can be used for cryptographic purposes.

Fig. 9 illustrates the FinFET-based 1-bit HOA design. As shown, the inverter forms the core building block of the proposed architecture. The device dimensions, including the channel length and width used in the simulation, are also specified in the figure.

7 Experimental Results↩︎

This section presents the simulation results for the designs of Hybrid Oscillator Arbiter PUF and the Arbiter PUF. A comparison of the designs is performed and evaluated for integrating the architecture into the wearable medical designs for a robust security.

7.1 Experimental Setup↩︎

The models from [62] were used for simulating the HOA PUF. The FinFET parameters used for the simulation are given in Table 2. The same parameters were taken for all the transistors across all the stages of the ROs. Manufacturing variations were simulated using Monte Carlo simulations. The nominal values presented in Table 2 were varied 10 % to simulate the manufacturing variations. The characteristics of the inverter used in the proposed design are shown in Fig. 10.

7.2 Performance Evaluation↩︎

As mentioned in the previous sections, not all the keys generated by the PUF can be used for cryptographic purposes. The following FoMs must be satisfied before they can be used reliably:

• Uniqueness

• Reliability

• Average Power Consumed

7.2.1 Uniqueness↩︎

Uniqueness is the PUF’s property to generate a unique key for that specific module. It can be categorized as two types of Uniqueness:

• Intra-Uniqueness - Given a single PUF module \(P_1\), every challenge given must produce a unique response.

• Inter-Uniqueness - When the same challenge input is given to multiple PUF modules, every module is expected to produce a unique response.

Uniqueness of a PUF is calculated using hamming distance. When two binary keys are considered, the number of bit positions they differ from each other is the hamming distance between the two keys. The ideal hamming distance between the considered keys must be 50 %.

Fig. 11 shows the signal frequencies generated by the ROs in the PUF module. This helps analyze the variation captured by the oscillators in the HOA PUF. Fig. 12 shows the uniqueness of all three PUF architecutures, the RO PUF, the Arbiter PUF and the HOA PUF. RO PUF and Arbiter PUF uniqueness is taken as a benchmark to evaluate the proposed HOA PUF. The average uniqueness of Arbiter PUF is 50.30 %, and the average uniqueness of the RO PUF is 50.50 %. Compared to these, the keys generated by the HOA PUF show a hamming distance of 51.30 %. All the three values are closer to the ideal value, 50 %, but the number of keys that are closer to the ideal value are more in the proposed HOA PUF. This shows the HOA PUF successfully captures the manufacturing variations in the circuit.

7.2.2 Reliability↩︎

Reliability is the ability of a PUF module to generate the same response for a given challenge despite the effects of circuit aging and environmental variations. Once the circuit is fabricated and deployed in a mission-critical application or consumer applications, it is expected to maintain consistent performance throughout the product’s operational lifetime. Cryptographic applications, in particular, demand a high degree of reliability and robustness, as the loss or alteration of a cryptographic key may result in data loss and, in some cases, irreversible consequences. Therefore, a PUF is expected to consistently reproduce the same key under varying environmental conditions, including fluctuations in power supply voltage and temperature.

Fig. 13 shows the simulation results of the reliability of the PUF architectures. The reliability of the PUF is also measured using hamming distance. During simulation, the same challenge is given to the PUF under temperature and power supply variations. As shown in the figure, the error rate of the HOA PUF is 2.35 %, RO PUF is 1.32 %, and Arbiter PUF is 1.8 % which are closer to the ideal values of 0 %.

7.2.3 Average Power↩︎

Wearable devices require ultra low power operation for a longer battery life. The power consumption of a PUF module plays a crucial role in its integration into applications in wearable technology. The average power consumed is the average of the total power consumed by the module over the period of key generation. In addition to wearable devices, the power consumption also plays an major role in the integration of this PUF design into resource-constrained environments, including smart healthcare and smart city applications.

The average power consumption of all three PUF architectures is shown in Fig. 14. The Arbiter PUF has 16 stages of Multiplexers and HOA PUF has 7 stages of inverters. The RO PUF and the HOA PUF have the same number of inverters with the only difference being an additional counter and comparator. The benchmark results were generated for both the RO PUF and the Arbiter PUF. RO PUF consumes about 3.5 \(\mu\)W and the arbiter PUF consumes about 2.5 \(\mu\)W. The HOA PUF on the other hand, consumes about 2.7 \(\mu\)W to generate 1 key.

7.3 Analysis of PUF Architectures↩︎

Table 4 shows the characterization of the proposed HOA PUF and a comparison with the other two architectures, RO PUF and Arbiter PUF. The uniqueness of the HOA PUF is about 51.3 % compared to the RO PUF, which is 50.4 % and the arbiter PUF, which is 50.3 %, as shown in the table. Although the average uniqueness of the RO PUF and the Arbiter PUF are closer to the ideal value of 50 %, as mentioned before, the standard deviation is higher in keys generated by the other two architectures. In addition to the lower standard deviation of average uniqueness, the error rate of the HOA PUF is 2.35 %. The average power consumption of the HOA PUF is also significantly lower compared to the other two architectures, and Arbiter PUF in particular which is about 10 \(\times\) higher than the HOA PUF. As the Arbiter PUF does not contain a multiplexer dedicated to selection of the individual components, the key generation time is much higher in the arbiter PUF. But there is also a trade off of the power consumption in the Arbiter PUF.

8 Conclusion and Future Research↩︎

This paper presented the analysis of two designs of PUF, Arbiter PUF and Hybrid Oscillator Arbiter PUF for integration into wearable devices. These wearable devices are low power devices that are incapable of performing high cryptographic tasks. Introducing such a PUF module to these devices helps generate keys and eliminates the need to store the keys. Depending on the PUF module architecture, it can generate any length of keys, and, if necessary, the PUF module is reconfigurable in some cases. The power consumption of Arbiter PUF is 25 \(\mu\)W and HOA PUF is 2.7 \(\mu\)W. The uniqueness of the PUF modules is also 51.3 % and 50.3 % which are near the ideal values. These two designs are ideal to be implemented in an appropriate IoT ecosystem to increase security. The future directions of this research include implementing PUF designs that are capable of more reconfigurability and ultra-low power design. Moreover, these designs will be integrated into an IoT ecosystem and a prototype will be designed for further analysis.

9 Acknowledgments↩︎

The preliminary research has been presented with the 32nm FinFETs in the following peer-reviewed conference [34] and has been changed to the 14nm FinFETs in the current paper.

Authors’ Biographies↩︎

Venkata P. Yanambaka received the Bachelor of Technology degree in Computer Science and Engineering from Priyadarshini College of Engineering and Technology, Nellore, India, the Master of Science degree in Computer Engineering from the University of North Texas, Denton, TX, and the Ph.D.degree in Computer Science and Engineering from the University of North Texas, Denton, TX, in 2019, under the supervision of Dr.Saraju P.Mohanty. His dissertation, titled “Exploring Physical Unclonable Functions for Efficient Hardware Assisted Security in IoT,” was awarded the Best Poster Award at IEEE MetroCon 2017. He is currently an Assistant Professor of Computer Science at Texas Woman’s University, Denton, TX. His research interests are in the Internet of Things (IoT), hardware-assisted security primitives, Physical Unclonable Functions (PUFs), and security in IoT architectures. He has authored over 50 peer-reviewed publications, including multiple journal and transaction articles and a book chapter. He has served as a reviewer for several peer-reviewed journals and conferences. He has been an active member of IEEE since 2012.

Uma Choppali Uma Choppali received her bachelor’s degree in science and education from the Regional Institute of Education, Bhubaneswar, India, in 1999, the master’s degree in physics from the University of South Florida, USA, in 2004, and the Ph.D. degree in materials science and engineering from the University of North Texas, USA, in 2006. She is a Faculty Member with Dallas College (Eastfield Campus), Mesquite, TX, USA. She has authored a dozen research articles. Her Google Scholar H-index is 12 and i10-index is 13 with 2275 citations. She is a regular reviewer of several international journals and conferences.

Saraju Mohanty received the bachelor’s degree (Honors) in electrical engineering from the Orissa University of Agriculture and Technology, Bhubaneswar, in 1995, the master’s degree in Systems Science and Automation from the Indian Institute of Science, Bengaluru, in 1999, and the Ph.D. degree in Computer Science and Engineering from the University of South Florida, Tampa, in 2003. He is a Professor with the University of North Texas. His research is in “Smart Electronic Systems’’ which has been funded by National Science Foundations (NSF), Semiconductor Research Corporation (SRC), U.S. Air Force, NIDILRR, IUSSTF, and Mission Innovation. He has authored 600 research articles, 5 books, and 10 granted and pending patents. His Google Scholar h-index is 68 and i10-index is 338 with 19,000 citations. He is regarded as a visionary researcher on Smart Cities technology in which his research deals with security and energy aware, and AI/ML-integrated smart components. He introduced the Secure Digital Camera (SDC) in 2004 with built-in security features designed using Hardware Assisted Security (HAS) or Security by Design (SbD) principle. He is widely credited as the designer for the first digital watermarking chip in 2004 and first the low-power digital watermarking chip in 2006. He is a recipient of 21 best paper awards, Fulbright Specialist Award in 2021, IEEE Consumer Electronics Society Outstanding Service Award in 2020, the IEEE-CS-TCVLSI Distinguished Leadership Award in 2018, and the PROSE Award for Best Textbook in Physical Sciences and Mathematics category in 2016. He has delivered 33 keynotes and served on 15 panels at various International Conferences. He has been serving on the editorial board of several peer-reviewed international transactions/journals, including IEEE Transactions on Big Data (TBD), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Transactions on Consumer Electronics (TCE), and ACM Journal on Emerging Technologies in Computing Systems (JETC). He has been the Editor-in-Chief (EiC) of the IEEE Consumer Electronics Magazine (MCE) during 2016-2021. He served as the Chair of Technical Committee on Very Large Scale Integration (TCVLSI), IEEE Computer Society (IEEE-CS) during 2014-2018 and on the Board of Governors of the IEEE Consumer Electronics Society during 2019-2021. He serves on the steering, organizing, and program committees of several international conferences. He is the steering committee chair/vice-chair for the IEEE International Symposium on Smart Electronic Systems (IEEE-iSES), the IEEE-CS Symposium on VLSI (ISVLSI), and the OITS International Conference on Information Technology (OCIT). He has supervised 3 post-doctoral researchers, 21 Ph.D. dissertations, 29 M.S. theses, and 41 undergraduate projects. received the bachelor’s degree (Honors) in electrical engineering from the Orissa University of Agriculture and Technology, Bhubaneswar, in 1995, the master’s degree in Systems Science and Automation from the Indian Institute of Science, Bengaluru, in 1999, and the Ph.D. degree in Computer Science and Engineering from the University of South Florida, Tampa, in 2003. He is a Professor with the University of North Texas. His research is in”Smart Electronic Systems’’ which has been funded by National Science Foundations (NSF), Semiconductor Research Corporation (SRC), U.S. Air Force, NIDILRR, IUSSTF, and Mission Innovation. He has authored 600 research articles, 5 books, and 10 granted and pending patents. His Google Scholar h-index is 68 and i10-index is 338 with 19,000 citations. He is regarded as a visionary researcher on Smart Cities technology in which his research deals with security and energy aware, and AI/ML-integrated smart components. He introduced the Secure Digital Camera (SDC) in 2004 with built-in security features designed using Hardware Assisted Security (HAS) or Security by Design (SbD) principle. He is widely credited as the designer for the first digital watermarking chip in 2004 and first the low-power digital watermarking chip in 2006. He is a recipient of 21 best paper awards, Fulbright Specialist Award in 2021, IEEE Consumer Electronics Society Outstanding Service Award in 2020, the IEEE-CS-TCVLSI Distinguished Leadership Award in 2018, and the PROSE Award for Best Textbook in Physical Sciences and Mathematics category in 2016. He has delivered 33 keynotes and served on 15 panels at various International Conferences. He has been serving on the editorial board of several peer-reviewed international transactions/journals, including IEEE Transactions on Big Data (TBD), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Transactions on Consumer Electronics (TCE), and ACM Journal on Emerging Technologies in Computing Systems (JETC). He has been the Editor-in-Chief (EiC) of the IEEE Consumer Electronics Magazine (MCE) during 2016-2021. He served as the Chair of Technical Committee on Very Large Scale Integration (TCVLSI), IEEE Computer Society (IEEE-CS) during 2014-2018 and on the Board of Governors of the IEEE Consumer Electronics Society during 2019-2021. He serves on the steering, organizing, and program committees of several international conferences. He is the steering committee chair/vice-chair for the IEEE International Symposium on Smart Electronic Systems (IEEE-iSES), the IEEE-CS Symposium on VLSI (ISVLSI), and the OITS International Conference on Information Technology (OCIT). He has supervised 3 post-doctoral researchers, 21 Ph.D. dissertations, 29 M.S. theses, and 41 undergraduate projects.

References↩︎