1 Introduction↩︎

Modern workloads keep demanding more compute than a single die can provide, and 3D integration is one architectural response: multiple active tiers stack vertically so on-chip compute and cache density grow without enlarging the footprint [1].

Stacking has a cost. Power dissipates into a smaller volume, so a 3D stack heats up faster than a planar die. Once the peak die temperature \(T_{\max}\) crosses a safe threshold, the chip throttles its clock to protect itself. The useful throughput is no longer the nominal \(\text{IPC}\cdot f_0\) that a simulator reports, but the thermally-derated \(\text{IPC}\cdot f(T_{\max})\) delivered on silicon, which is the BIPS metric [2]. What \(f(T_{\max})\) ends up being on a given configuration depends on the joint power map across tiers, on which macro sits above which, and on where the hottest concentration of switching activity lands in plane. The 3D layout decides all of this, and an architectural simulator sees none of it before architecture commitment.

Yet early-stage 3D-IC exploration still picks candidates from the simulator’s IPC alone. Simulators such as gem5 [3], [4] and SimpleScalar [5] assume idealized interconnect latencies and a fixed clock. The architect sees an IPC per candidate but no per-block power map, no cache cycle counts derived from real array geometry, and no layout under which \(T_{\max}\) could be defined. This choice can fail in a 3D stack: a design that maximizes IPC under ideal timing can also be the design that concentrates the most power in the hottest tier, throttles the most, and delivers among the lowest realized BIPS.

This is a shift-left problem in 3D-IC CAD: the layout-driven physical effects that determine realized BIPS must be exposed to early-stage architectural exploration, not deferred until post-floorplan sign-off. What is missing is a path that turns the simulator’s logic-level output into a physical block representation, plus an optimizer that uses that representation to choose a layout instead of inheriting whatever default the thermal sign-off tool reads from disk.

Two prior threads each address half of this gap. 3D thermal-aware floorplanners [6]–[11] optimize a linear cost \(w_{\text{HPWL}}\!\cdot\!\text{HPWL}+w_{\text{thermal}}\!\cdot\!T_{\max}\) (half-perimeter wirelength, HPWL) or a close variant. The weights are not derived from the architectural quantity the system delivers, so the chosen layout is optimal for a surrogate, not for realized BIPS, and the resulting frequency constraints are never fed back to the architectural simulator. 3D thermal frameworks such as Cool-3D [12] and HotGauge [13], and runtime schedulers such as HotLEGO [14], focus on thermal management with the floorplan held fixed: they manage temperature through dynamic voltage and frequency scaling (DVFS) or task migration on a layout the flow takes as input. Designers therefore still lack a way to answer the concrete question of what BIPS a given microarchitecture and stack deliver under their BIPS-maximizing layout, which depends on physical placement that the simulator never exposes.

To solve these problems, we present CLIP-3D, summarized in 1. The figure frames the gap as two existing regimes. The Quick regime evaluates a candidate using fast architectural simulation alone (gem5 [3], [4], SimpleScalar [5]) and reports PPA without thermal. The Traditional regime invokes the full McPAT [15], CACTI [16], and HotSpot [17]–[19] stack to produce PPAT, but is orders of magnitude slower per candidate, so it cannot drive a design-space exploration. CLIP-3D answers the three open questions raised by the figure. It lifts each architectural candidate into the PPAT inputs a 3D layout optimizer needs (per-block power map, cache access cycles, and 3D thermal-stack conductance) with one gem5 pass and one HotSpot solve per candidate, evaluates the layout objective in closed form rather than by repeated thermal simulation, and feeds the resulting realized BIPS back to architectural exploration before commitment. Our main contributions are summarized as follows:

• We bridge architectural simulation and 3D layout with a lifting pipeline. It converts a simulator’s IPC trace into the per-block power, cache access cycles, and 3D thermal-stack conductance a layout optimizer needs, with no changes to the upstream simulator (3).

• We derive a closed-form expression for the thermally sustainable clock. It is exact under HotSpot’s steady-state model and replaces the temperature-frequency fixed-point iteration that thermal-aware evaluators normally run (3.4).

• We build an analytical 3D thermal-aware floorplanner that optimizes realized BIPS directly. The objective needs no HPWL-plus-temperature surrogate weights and no in-loop HotSpot calls, both of which gate prior frameworks (3.5).

• We evaluate CLIP-3D on five workloads under two cooling envelopes. It sits on the wall-time vs.realized-BIPS Pareto frontier against three baselines, and a ranking diagnostic shows that IPC-only selection becomes roughly uncorrelated with realized BIPS once cooling binds (4).

2 Preliminaries↩︎

This section walks through the lifting pipeline CLIP-3D builds on, the 3D IC structure that makes layout a first-order architectural decision, and the design-selection problem we solve via the two-stage formulation of 2.3.

2.1 Architecture-to-Physical Lifting Pipeline↩︎

CLIP-3D drives four open-source EDA tools: gem5 [3], [4], McPAT [15], HotSpot [17], and CACTI [16]. The pipeline turns a candidate architecture into the block-level physical inputs a 3D layout optimizer needs.

A candidate design is \(\mathbf{d}=(\mathbf{a},\mathbf{p})\). \(\mathbf{a}\) is the architectural vector (core count, L1D/L2 sizes, associativity, pipeline parameters). \(\mathbf{p}\) is the physical vector (die area, per-block tier assignment, in-plane positions). For workload \(\mathbf{w}\), the lifting starts with a gem5 run that uses an out-of-order core under idealized cache and interconnect latencies. This first run reports a nominal IPC, denoted \(\text{IPC}_1\), and per-block activity statistics (cache accesses, misses, branch events, write-backs) that drive every subsequent stage.

McPAT consumes those statistics and returns per-block dynamic power \(P_{\text{dyn},b}\), leakage power \(P_{\text{leak},b}\), and an architecture-derived block area \(A_b\). In parallel, CACTI characterizes the cache hierarchy and converts L1D/L2 geometry into access cycles. Combined with a discrete through-silicon-via (TSV) hop model for inter-tier wiring (3), the CACTI cycles form a latency vector \(\mathbf{L}(\mathbf{d})\) that captures both on-die cache timing and cross-tier communication cost. Back-annotating \(\mathbf{L}(\mathbf{d})\) into the cache hierarchy and rerunning gem5 returns a calibrated IPC, denoted \(\text{IPC}_2\), that reflects the actual memory-system delay.

The per-block power map is rasterized onto the 3D thermal stack defined by \(\mathbf{p}\) and handed to HotSpot, which solves the steady-state heat equation and returns the peak die temperature \(T_{\max}(\mathbf{d};\mathbf{w})\). Once \(T_{\max}\) exceeds a safe operating threshold \(T_{\text{safe}}\), the hardware throttles its clock to avoid thermal damage. We model this throttle with the standard piecewise-linear form \[f(T)=\max\!\Bigl(f_{\min},\; f_0\bigl[1-\alpha\,\max\!\bigl(0,\;T-T_{\text{safe}}\bigr)\bigr]\Bigr), \label{eq:throttle}\tag{1}\] with nominal clock \(f_0\), throttling slope \(\alpha\), and floor frequency \(f_{\min}\); specific parameter values are stated in 4.1. 3.4 shows that the linearity of HotSpot’s steady-state operator and the CMOS power-frequency decomposition collapse \(f(T_{\max})\) into a closed-form expression in \(\mathbf{a}\) and \(\mathbf{p}\), which lets the floorplanner of 3.5 optimize layout for realized BIPS without invoking HotSpot inside its inner loop.

The realized throughput of a design is the thermally-derated BIPS metric [2], \[\text{BIPS}_2(\mathbf{d};\mathbf{w}) \;=\; \text{IPC}_2(\mathbf{d};\mathbf{w}) \cdot f\!\bigl(T_{\max}(\mathbf{d};\mathbf{w})\bigr), \label{eq:bips}\tag{2}\] which both stages of CLIP-3D compute and optimize.

2.2 3D IC Structure↩︎

CLIP-3D targets monolithic or TSV-based 3D stacks with \(N_t\) active device tiers stacked vertically between a bottom substrate and a top heat sink. Three physical features distinguish this setting from a planar die.

First, vertical interconnects are discrete. Cross-tier signals go through TSVs whose delay, area, and parasitics differ materially from intra-tier wires [20], and the number of TSV hops between two blocks depends on their \((\text{tier},x,y)\) assignment. A latency model that ignores hop discreteness and uses a continuous linear-distance proxy systematically misestimates cross-tier access time.

Second, vertical thermal coupling is asymmetric. Heat dissipates primarily through the top heat sink, so lower tiers accumulate heat from all tiers above them. The peak temperature on the hottest tier therefore depends on the joint power map across tiers, not on any single tier in isolation [21], and is decided as much by which macros sit on which tier as by how much power each macro draws.

Third, tier-aware floorplanning changes the design variable. The physical vector \(\mathbf{p}\) assigns each microarchitectural block \(b\!\in\!B\) to a \((\text{tier},x,y)\) position under non-overlapping, die-area, and tier-consistency constraints. This is a richer design space than a 2D floorplan, and a different choice of \(\mathbf{p}\) shifts \(T_{\max}\) and the realized BIPS even at fixed \(\mathbf{a}\).

These three features together mean the map \(\mathbf{p}\!\to\!(\mathbf{L},T_{\max})\) is neither separable across tiers nor well-approximated by linear-distance proxies. A meaningful evaluation of architectural choice \(\mathbf{a}\) has to know the layout \(\mathbf{p}\) that choice will be deployed under, which motivates the two-stage formulation that the next subsection makes precise.

2.3 Problem Formulation↩︎

1 collects the symbols introduced in [subsec:flow,subsec:3dic_struct] for reference throughout the paper.

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For workload \(\mathbf{w}\) and an admissible architectural set \(\mathcal{A}\), CLIP-3D selects the architecture whose realized BIPS, evaluated under the layout that maximizes that BIPS, is highest: \[\mathbf{a}^{\star}(\mathbf{w}) \;=\; \arg\max_{\mathbf{a}\in\mathcal{A}}\; \underbrace{\max_{\mathbf{p}\in\mathcal{P}(\mathbf{a})}\; \text{IPC}_2(\mathbf{a},\mathbf{p};\mathbf{w})\cdot f\!\bigl(T_{\max}(\mathbf{a},\mathbf{p};\mathbf{w})\bigr)}_{\mathbf{p}^{\star}(\mathbf{a};\mathbf{w}),\;\text{the inner layout problem solved by~\Cref{sec:sec:analytical-placer}}}, \label{eq:objective}\tag{3}\] subject to a hard thermal bound \(T_{\max}(\mathbf{a},\mathbf{p};\mathbf{w})\!\le\!T_{\text{hard}}\) at the junction reliability limit and physical feasibility of the 3D floorplan (non-overlapping blocks, die-area bound, tier-assignment consistency captured by \(\mathcal{P}(\mathbf{a})\)). The inner \(\max_\mathbf{p}\) defines the layout problem CLIP-3D’s analytical floorplanner solves for each candidate architecture. The outer \(\arg\max_\mathbf{a}\) is the architectural-DSE loop that consumes the floorplanner’s output. A baseline shelf-pack layout, used in our comparisons, is recovered as the special case where \(\mathbf{p}\) is fixed by deterministic rule rather than optimized against the realized BIPS.

To quantify how much layout optimization changes the architectural ranking, we additionally report a three-level diagnostic over the same design set:

• Level-0 (IPC-only): rank designs by \(\text{IPC}_1\) alone. Lifting is ignored entirely.

• Level-1 (thermal-only): rank designs by \(\text{IPC}_1 \cdot f(T_{\max})\). Only the thermal output of the lifting is used.

• Level-2 (lifted): rank designs by \(\text{IPC}_2 \cdot f(T_{\max})\). The full lifting output is used.

The Kendall-\(\tau\) [22] between any pair of these rankings, \(\tau=(C-D)/\binom{n}{2}\) with \(C\) and \(D\) counting concordant and discordant design pairs, quantifies how much ranking signal is forfeited when a stage of the pipeline is dropped. We use this diagnostic in 4 to motivate why both lifting and the layout optimization on top of it are needed.

3 Methodology↩︎

CLIP-3D solves the two-stage problem of 3 in three stages (2). First, an architecture-to-physical lifting pipeline turns each candidate \(\mathbf{a}\) into the block-level inputs (per-block dynamic and leakage power, cache access cycles, 3D thermal-stack conductance) that a 3D layout optimizer needs ([subsec:overview,subsec:thermal_loop,subsec:delay_loop]). Second, the linearity of HotSpot’s steady-state operator together with the standard CMOS power-frequency decomposition collapse the throttled clock \(f(T_{\max})\) into a closed-form expression in those block-level inputs (3.4), which can be evaluated without re-invoking HotSpot. Third, an analytical 3D thermal-aware floorplanner consumes the lifted block representation and embeds the closed form directly inside its objective, so the inner \(\mathbf{p}^{\star}(\mathbf{a})\) of 3 is solved for the same realized BIPS the rest of the pipeline scores designs on (3.5); symbols follow 1 throughout.

3.1 Overview and Per-Configuration Lifting↩︎

The lifting stage decomposes a candidate \(\mathbf{a}\) into the two block-level inputs that decide its realized BIPS: a per-block power map plus 3D-stack thermal model that determines \(T_{\max}\) and therefore \(f(T_{\max})\), and a CACTI-calibrated cache-and-topology latency vector that is back-annotated into a second gem5 pass for a physically realistic \(\text{IPC}_2\).

• The thermal lifting (3.2) maps per-block power and the candidate’s stack geometry onto a 3D-stack power grid that HotSpot [17] can solve for the peak die temperature \(T_{\max}(\mathbf{d})\), which drives \(f(T_{\max})\) via the closed-form model of 3.4.

• The latency lifting (3.3) maps the architectural configuration into a discrete latency vector \(\mathbf{L}(\mathbf{d})\): CACTI-calibrated cache access time plus a shared-cache arbitration term, an integer TSV-hop term, and a pipeline constant. \(\mathbf{L}(\mathbf{d})\) is back-annotated into a second architectural simulation for a calibrated \(\text{IPC}_2\).

The two lifted outputs are methodologically disjoint: the floorplan modulates temperature only, and the latency vector depends on architectural and topological quantities only. This separation is what lets CLIP-3D replace the linear-distance wire-delay proxies of prior flows with a parameter-free discrete model, and it lets the floorplanner of 3.5 treat \(\mathbf{L}\) as a per-architecture constant while it optimizes layout for \(T_{\max}\).

3.1.0.1 Shared front-end: architecture \(\to\) power and \(\text{IPC}_1\)

Both lifted outputs start from a single upstream pass. We run gem5 [3] in syscall-emulation mode with an out-of-order X86 core (\(4\)-wide dispatch, \(192\)-entry ROB, split L1 I/D) clocked at \(f_0{=}\SI{2.0}{\giga\hertz}\), with the cache hierarchy set from the architectural vector \(\mathbf{a}\) (L1 associativity \(2\), L2 associativity \(8\)). Workloads are warmed up for \(10^{8}\) instructions and measured over the following \(5{\times}10^{8}\) instructions per core. The resulting stats.txt is translated into McPAT’s activity schema [15] configured at the \(\SI{45}{\nano\meter}\) node (matching the Cool-3D [23] baseline) to emit per-block dynamic, leakage, and gate-leakage power \(P_i\) and block areas \(A_i\). This pass produces \(\text{IPC}_1(\mathbf{d})\) (the nominal IPC under idealized cache timing, used only as the Level-0 score of 2.3) and the per-block power and area trace consumed by the thermal lifting.

3.1.0.2 Lifted output

The two lifted outputs combine into the realized throughput \[\text{BIPS}_2(\mathbf{d};\mathbf{w}) \;=\; \text{IPC}_2(\mathbf{d};\mathbf{w}) \cdot f\!\bigl(T_{\max}(\mathbf{d};\mathbf{w})\bigr), \label{eq:bips95method}\tag{4}\] which reproduces 2 of the preliminaries. In addition to \(\text{BIPS}_2\), we retain \(\text{IPC}_1\) and \(T_{\max}\) so that the Level-0, Level-1, and Level-2 rankings of 2.3 can all be reported over the same design set. The Kendall-\(\tau\) between each pair quantifies how much ranking signal each additional lifting stage contributes; we use this decomposition in 4 as a diagnostic on why the lifting is necessary in the first place. The analytical floorplanner of 3.5 then takes the lifted block representation as its input.

3.1.0.3 Per-configuration cost

Each configuration requires two gem5 invocations (dominated by the out-of-order simulation at \(\mathcal{O}(I)\) per workload), one McPAT call (\(\mathcal{O}(|B|)\)), one HotSpot call per layout queried (\(\mathcal{O}(G^2)\) for a \(G{\times}G\) grid), and an \(\mathcal{O}(1)\) CACTI lookup amortized over the design-space exploration (DSE). gem5 dominates; per-configuration wall time of the lifting stage is \(\sim\!\SI{80}{\second}\) on our workstation, and the closed-loop sweep across both cooling envelopes (4.1) completes in about \(1\,\mathrm{h}\) per envelope at 16-way parallelism on 32 physical cores. Per-worker scratch directories isolate McPAT, CACTI, and HotSpot intermediate files so the 24-way speedup runs without cross-worker contention on shared output paths.

3.2 Thermal Lifting: Stack, Floorplan Materialization, and HotSpot↩︎

Given the per-block power and area trace from the shared front-end, the thermal lifting produces \(T_{\max}(\mathbf{d})\) for any layout candidate by rasterizing that layout onto a uniform grid and running HotSpot to steady state. For diagnostic experiments that fix layout ([subsec:ranking_baseline,subsec:ranking_stressed]) and as the baseline against which 3.5 is compared, we use a deterministic shelf-pack rule. The analytical floorplanner of 3.5 replaces this rule with an L-BFGS-B [24] solver whose objective is the realized BIPS itself.

3.2.0.1 Shelf-pack baseline floorplan

The baseline layout is a deterministic shelf-pack: a row-based packing rule from VLSI placement, used as the default convention in architectural-stage 3D-DSE flows that lack a thermal-aware placer. It is fully determined by the core count and die geometry, and is what every comparison in the experimental section uses. Blocks of each core are packed as a rectangular cluster on the bottom die according to a fixed rule: a \(1\)-core configuration is centered, \(2\) cores are split left and right, and \(4\) cores occupy either the four quadrants (on \(\SI{12}{\mm}^2\) dies, where quadrant area is sufficient to hold the largest per-core cluster) or two side-by-side strips (on the tighter \(\SI{10}{\mm}^2\) dies). The shared L2 and any other memory-side blocks are placed on the top die, which sits closer to the heat sink in the package stack; this mirrors the physical organization used in commercial 3D-stacked products where the cache tier is stacked on top of the compute tier to exploit the shorter thermal path out of the stack. The output is the per-block tuple \((x_i,y_i,w_i,h_i,z_i)\) with \(z_i\in\{0,1\}\) denoting tier assignment in the two-tier stack.

Die area not covered by any microarchitectural block is filled with dead-silicon tiles carrying zero power. Leaving those regions empty in the power trace would cause HotSpot to model them as insulating voids and overestimate the peak temperature; the silicon filler restores the correct lateral heat-spreading path without introducing any heat source of its own.

3.2.0.2 Grid power map

Following the Cool-3D pipeline, we avoid the common HotSpot “block count mismatch” pitfall by rasterizing block powers onto a uniform \(G{\times}G\) grid per tier via area-overlap accounting: \[\text{grid}_z[\,c_y,c_x\,] \;+=\; \sum_{i\in B_z} \frac{\mathrm{overlap}\bigl(b_i,\,\mathrm{cell}_{c_x,c_y}\bigr)}{A_i}\cdot P_i, \label{eq:gridmap}\tag{5}\] where \(B_z\) is the block set on tier \(z\) and \(\mathrm{overlap}(\cdot)\) is the geometric intersection area. This produces a grid representation with identical shape across configurations with different block counts, allowing direct comparison of \(T_{\max}\) across designs. We use \(G{=}32\) in this work, giving \(\sim\!\SI{313}{\micro\meter}\) cell pitch on a \(\SI{10}{\mm}\) die, fine enough to resolve the fastest thermal gradient observed in our sweep, and at a grid resolution that keeps the per-ptrace line under HotSpot’s internal buffer limits.

3.2.0.3 HotSpot configuration

HotSpot is invoked in grid mode with detailed_3D enabled on a five-layer stack (interposer, bottom die, thermal interface material (TIM), top die, top TIM). We use the default Cool-3D package parameters: \(\SI{30}{\mm}\) spreader, \(\SI{60}{\mm}\) heat sink, natural-convection ambient of \(\SI{45}{\celsius}\), and a silicon thickness of \(\SI{50}{\micro\meter}\) per die. The steady-state solution yields the per-cell temperature grid, from which we define \(T_{\max}(\mathbf{d})=\max_{z,c_x,c_y}T_z[c_y,c_x]\). A design that cannot be cooled below \(T_{\text{safe}}\) even at \(f_{\min}\) is clipped at \(f_{\min}\) rather than removed from the search, so that the comparison across points stays monotone and there is no discontinuity at the feasibility boundary. The thermal lifting is then complete: the architectural vector \(\mathbf{a}\) and the physical vector \(\mathbf{p}\) jointly determine \(f(T_{\max})\) via the closed-form model derived in 3.4, which the floorplanner of 3.5 optimizes \(\mathbf{p}\) against on every candidate layout it considers.

3.3 Latency Lifting: CACTI-Calibrated Discrete Latency↩︎

The latency lifting calibrates IPC against cache and on-chip-network timing derived from device-level simulation, replacing the linear-distance wire-delay proxies used by prior flows.

3.3.0.1 CACTI-calibrated cache latency

For each cache geometry in our sweep, we run CACTI [16] at the \(\SI{45}{\nano\meter}\) node with the same technology parameters used by McPAT in the shared front-end (consistent node, consistent transistor model). The resulting access time in nanoseconds is converted into an integer gem5 cycle count at the nominal \(f_0{=}\SI{2.0}{\giga\hertz}\) clock (see 2). Because cache geometry is part of the architectural vector \(\mathbf{a}\), a single precomputed lookup table \(\ell_{\text{CACTI}}(s_{L1D},s_{L2})\) covers the entire design space without re-running CACTI during DSE.

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Access time in ns; area in \(\mathrm{mm}^2\). gem5 cycles are integer-rounded at \(f_0{=}\SI{2.0}{\giga\hertz}\).

3.3.0.2 Discrete topology penalties

On top of the CACTI access time, we add three integer penalties that correspond to the three dominant sources of on-chip communication delay in a 3D multi-core stack: \[\mathbf{L}(\mathbf{d}) \;=\; \underbrace{\ell_{\text{CACTI}}\bigl(s_{L1D},s_{L2}\bigr)}_{\text{cache access}} \;+\; \underbrace{(N_{\text{cores}}\!-\!1)}_{\text{L2 arbitration}} \;+\; \underbrace{2\cdot h_{\text{TSV}}}_{\text{inter-tier}} \;+\; \underbrace{1}_{\text{L1 pipe}}, \label{eq:latency95model}\tag{6}\] where each term is justified as follows.

• \(\ell_{\text{CACTI}}\) comes from 2. It already absorbs all intra-array wordline and bitline delay so no additional distance scaling is applied.

• The \((N_{\text{cores}}{-}1)\) term is a standard busy-waiting bound for an \(N\)-way shared last-level cache under the common MOESI-like coherence assumption, and matches the worst-case per-request arbitration delay reported by prior L2 miss studies [25].

• \(h_{\text{TSV}}\) is the integer number of TSV crossings on the critical path between the requester and the target L2 bank, derived from the floorplan’s tier-assignment vector \(\{z_i\}\). Each crossing adds \(2\) cycles, which matches the capacitive-load-limited traversal time of a \(\SI{50}{\micro\meter}\)-pitch TSV in \(\SI{45}{\nano\meter}\) silicon reported by [10].

• The trailing \(1\)-cycle term is the L1 pipeline stage, consistent with the gem5 SimpleMemory model.

\(\mathbf{L}(\mathbf{d})\) is back-annotated into gem5 by overriding the tag_latency, data_latency, and response_latency parameters of each cache node plus the xbar latency between L1 and L2. The second gem5 pass yields \(\text{IPC}_2(\mathbf{d})\) on the same workload trace.

3.3.0.3 Topology-only scope of \(\mathbf{L}(\mathbf{d})\)

\(\mathbf{L}(\mathbf{d})\) as defined in 6 captures only architectural and topology-level penalties (CACTI cache access, shared-L2 arbitration, integer TSV crossings, L1 pipeline). It is layout-invariant: it does not depend on block \((x,y)\) coordinates or intra-die wire distances. Three observations justify this decoupling quantitatively:

1. Scale of in-plane delay. At \(\SI{45}{\nano\meter}\) and \(\SI{2}{\giga\hertz}\), RC-limited wire propagation across a \(\SI{10}{\milli\meter}\) die is under \(\SI{500}{\pico\second}\), that is, one cycle. Compared to an L2 access of \(6\) to \(10\) cycles from 2, any in-plane term is below \(15\%\) of the dominant cache latency and well within the empirical IPC sensitivity we bound in 4.

2. Dominance of TSV capacitance. In a 3D stack, inter-tier physical distance is below \(\SI{100}{\micro\meter}\) and propagation delay is dominated by TSV driver capacitance, not wire length [10]. A discrete “cycles-per-hop” model captures this far more faithfully than a continuous distance-scaled proxy.

3. NoC hop convention. In modern multi-core fabrics, horizontal inter-core and core-to-L2 traffic is routed through router-based networks-on-chip whose per-hop delay is fixed by topology rather than by floorplan coordinates [26]. Linear distance is therefore already absent from the latency model of the fabric itself.

In summary, floorplan geometry enters the thermal lifting only, through the grid of 5 ; latency depends only on architectural and topological quantities through 6 . The two lifted outputs remain methodologically disjoint, and both feed into the realized BIPS through 4 . This disjointness is what lets the floorplanner of 3.5 treat \(\mathbf{L}(\mathbf{d})\) as a per-architecture constant while it varies \(\mathbf{p}\) to optimize \(T_{\max}\) without revisiting the latency model. A complementary layout-dependent in-plane wire-delay term, derived from the same Bakoglu–Meindl model, is introduced separately inside the floorplanner objective of 14 and integer-cycled into gem5 at the R2 back-annotation step of 4.4; it is not part of \(\mathbf{L}(\mathbf{d})\) above.

3.4 Closed-Form Frequency via Thermal-Operator Linearity↩︎

The piecewise-linear throttle of 1 is convenient, but its slope \(\alpha\) is a fitted constant that carries no direct physical meaning. We replace it with a closed-form expression by observing that the two physical quantities it compresses, the steady-state response of HotSpot and the power-frequency scaling of McPAT, are both linear. Composing them produces a temperature field whose dependence on \(f\) is equally transparent in closed form.

HotSpot’s steady-state solver discretizes the 3D heat equation on the per-tier grid and assembles a sparse thermal-conductance matrix \(\mathbf{G}_\theta\in\mathbb{R}^{N\times N}\) whose entries are determined entirely by the floorplan, material stack, TIM, and package. Solving \(\mathbf{G}_\theta\,\mathbf{T} = \mathbf{P} + \mathbf{G}_\theta\,T_{\text{amb}}\mathbf{1}\) is therefore equivalent to applying a fixed linear operator \[\mathbf{T} - T_{\text{amb}}\mathbf{1} \;=\; \mathbf{R}_\theta\,\mathbf{P}, \qquad \mathbf{R}_\theta \triangleq \mathbf{G}_\theta^{-1}, \label{eq:linear95operator}\tag{7}\] to the per-cell power vector \(\mathbf{P}\in\mathbb{R}^{N}\). The operator \(\mathbf{R}_\theta\) does not depend on \(\mathbf{P}\) or on \(f\); for a given 3D stack it is effectively a constant. On the McPAT side, per-block power is split into a dynamic component \(P_{\text{dyn},b}\) and a leakage component \(P_{\text{leak},b}\) (sub-threshold and gate combined). At fixed supply voltage, synchronous switching scales linearly with the clock frequency [27], while leakage is \(f\)-independent. After rasterization onto the thermal grid via 5 , the cell-level power vector therefore admits the exact decomposition \[\mathbf{P}(f) \;=\; \mathbf{P}_{\text{leak}} \;+\; \frac{f}{f_0}\,\mathbf{P}_{\text{dyn}}, \label{eq:power95decomp}\tag{8}\] where \(\mathbf{P}_{\text{leak}}\) and \(\mathbf{P}_{\text{dyn}}\) are both read off directly from the nominal-frequency output of the shared front-end.

Substituting 8 into 7 and applying superposition gives a temperature field that is affine in \(f\): \[\mathbf{T}(f) \;=\; T_{\text{amb}}\mathbf{1} \;+\; \mathbf{R}_\theta\,\mathbf{P}_{\text{leak}} \;+\; \frac{f}{f_0}\,\mathbf{R}_\theta\,\mathbf{P}_{\text{dyn}}. \label{eq:T95of95f}\tag{9}\] Every cell temperature traces a straight line in \(f\) whose intercept is the leakage-only self-heat map and whose slope is the dynamic-only self-heat map evaluated at \(f_0\). A single HotSpot invocation at \(f_0\) already yields \(\mathbf{T}(f_0)\). Evaluating 9 at any other frequency is \(\mathcal{O}(N)\) vector arithmetic, with no need to re-solve \(\mathbf{G}_\theta\) at each trial frequency.

In the absence of per-block leakage detail, a further simplification is both convenient and empirically accurate. Let \[\gamma \;\triangleq\; \frac{\sum_c P_{\text{leak},c}}{\sum_c \bigl(P_{\text{leak},c}+P_{\text{dyn},c}\bigr)}\] denote the grid-level leakage fraction, which McPAT reports per configuration. If the per-cell ratio \(P_{\text{leak},c}/P_c(f_0)\) is approximately uniform across the die, which is reasonable when logic and SRAM share the same process node, then \(\mathbf{P}_{\text{leak}}\approx\gamma\mathbf{P}(f_0)\) and \(\mathbf{P}_{\text{dyn}}\approx(1-\gamma)\mathbf{P}(f_0)\), and 9 collapses into a rigid scaling of a single map: \[\mathbf{T}(f) - T_{\text{amb}}\mathbf{1} \;=\; \Bigl[\gamma + (1-\gamma)\tfrac{f}{f_0}\Bigr]\bigl(\mathbf{T}(f_0) - T_{\text{amb}}\mathbf{1}\bigr). \label{eq:T95scalar}\tag{10}\] The scalar factor is the same at every cell and strictly positive, so the peak location is preserved across \(f\) and the peak temperature obeys \[T_{\max}(f) - T_{\text{amb}} \;=\; \Bigl[\gamma + (1-\gamma)\tfrac{f}{f_0}\Bigr]\bigl(T_{\max}(f_0) - T_{\text{amb}}\bigr). \label{eq:Tmax95of95f}\tag{11}\]

Setting \(T_{\max}(f)=T_{\text{safe}}\) in 11 and solving for \(f\) gives the highest clock frequency consistent with the thermal budget: \[f_{\text{sus}}(\mathbf{d}) \;=\; \max\!\left(f_{\min},\; \frac{f_0}{1-\gamma}\!\left[\frac{T_{\text{safe}}-T_{\text{amb}}}{T_{\max}(\mathbf{d};\,f_0)-T_{\text{amb}}} - \gamma\right]\right) \label{eq:fsus}\tag{12}\] when \(T_{\max}(\mathbf{d};f_0)>T_{\text{safe}}\), and \(f_{\text{sus}}(\mathbf{d})=f_0\) otherwise. Equation 12 replaces the fitted slope \(\alpha\) of 1 with two directly observable parameters: \(T_{\text{safe}}\), the dynamic thermal management (DTM) trigger used by commodity DVFS controllers (typically \(\SI{85}{\celsius}\) on server-class silicon), and \(\gamma\), the leakage fraction read straight out of McPAT. CLIP-3D uses this form as the definition of \(f(T_{\max})\) in the \(\text{BIPS}_2\) objective of 2 and in the ranking diagnostics of 4.

Two consequences follow. First, because 12 is closed-form in the single scalar \(T_{\max}(\mathbf{d};f_0)\), sweeping \(\gamma\) or \(T_{\text{safe}}\) at evaluation time costs \(\mathcal{O}(|\mathcal{D}|)\) scalar operations rather than \(|\mathcal{D}|\) fresh thermal simulations, and the per-configuration HotSpot solve of the thermal lifting is reused. Second, the uniform-\(\gamma\) assumption underlying 10 can be lifted without giving up the closed-form structure: evaluating 9 once with \(\mathbf{P}_{\text{dyn}}=\mathbf{0}\) and once with \(\mathbf{P}_{\text{leak}}=\mathbf{0}\) calibrates the leakage and dynamic self-heat maps separately, after which the per-cell affine form in \(f\) is exact. This two-point calibration costs one extra HotSpot solve per configuration and serves as the principled fallback when logic and cache have markedly different leakage profiles across block classes.

3.5 Analytical 3D Thermal-Aware Floorplanner with Closed-Form \(f_{\text{sus}}\) Inside the Objective↩︎

The lifted block representation of [subsec:overview,subsec:thermal_loop,subsec:delay_loop] and the closed-form sustainable frequency of 12 together make the inner \(\mathbf{p}^{\star}(\mathbf{a})\) of 3 solvable analytically. We can search over \(\mathbf{p}\) for the layout that maximizes the realized BIPS itself, rather than minimizing a surrogate that approximates it. Prior 3D thermal-aware floorplanning frameworks (e.g., [11]) optimize a linear cost \(\,w_{\text{HPWL}}\!\cdot\!\text{HPWL}+w_{\text{thermal}}\!\cdot\!T_{\max}\,\) whose weights \((w_{\text{HPWL}},w_{\text{thermal}})\) are not derivable from the architectural quantity the system actually delivers. The optimum of that linear cost is in general not the optimum of \(\text{BIPS}_2 = \mathrm{IPC}\!\cdot\!f_{\text{sus}}(T_{\max}(\mathbf{d}),\gamma)\), and the gap is workload- and regime-dependent (4). The linear cost also stays positive on configurations with thermal headroom, where there is no \(T_{\max}\) pressure to relieve, so small layout perturbations can move the score in either direction and produce false-positive “improvements”. We therefore embed 12 directly in the floorplanner’s objective, so cross-tier macro assignment and in-plane placement are co-optimized for the same realized BIPS the rest of the pipeline scores designs on.

3.5.0.1 Decision variables.

For a \(K\)-tier stack, let \(z\!\in\!\{0,1\}^M\) be the cross-tier assignment of \(M\) movable macros (the L2 cache and, optionally, large core tiles) and let \((x,y)\!\in\!\mathbb{R}^{2M}\) be their in-plane coordinates. We treat \(z\) discretely via Fiduccia–Mattheyses-style 2-way enumeration over the \(K^M\) tier assignments and run the continuous L-BFGS-B optimization conditioned on each candidate. For the 4-core 2-tier P1 stack of our experiments (\(K\!=\!2\), \(M\!=\!1\) since the 4 cores are pre-grouped into a tile and only the L2 macro is free to migrate), this enumeration reduces to two L-BFGS-B runs and is exact. For larger \(M\) a standard FM partitioner [28] replaces the enumeration without changing the rest of the pipeline.

3.5.0.2 Block-level thermal proxy.

Within the inner optimization loop we need a temperature signal that is monotone in the right direction (hot blocks clustered together or relegated to the bottom tier produce a higher predicted \(T_{\max}\)) and differentiable in \((x,y)\), but not a high-fidelity simulator. We aggregate the per-sub-block \(\texttt{ptrace}\) entries into per-tile centroids \((x_t,y_t)\) with summed power \(P_t\), and predict \[\begin{align} \hat{T}_{\max}(x_{L2}, y_{L2}; z) \;=\;& T_{\text{amb}} + R_{\text{conv}}P_{\text{tot}} \\ &{}+\, \alpha\,\max_i\!\sum_j P_j\,\mathcal{K}(d_{ij})\,w(z_i,z_j) \\ &{}+\, \beta\!\sum_{j\in\text{bot}}\!P_j, \end{align} \label{eq:tmax95proxy}\tag{13}\] where \(\mathcal{K}(d)\!=\!1/\sqrt{1+(d/L_c)^2}\) is a smooth Pythagorean kernel with \(L_c\) set to the die half-width, \(w(z_i,z_j)\!\in\!\{1,w_{\text{cross}}\}\) down-weights cross-tier pairs, \(R_{\text{conv}}P_{\text{tot}}\) is the exact lumped-heatsink rise, and \((\alpha,\beta)\) are unit-conversion constants chosen once so \(\hat{T}_{\max}\) lands in the \(80\) to \(110\,^\circ\text{C}\) regime where 12 has non-trivial response. The proxy is intentionally crude: only its gradient direction drives the optimizer, and the absolute \(T_{\max}\) that enters all paper-reported numbers comes from the validation HotSpot pass below. This separation lets the inner loop be HotSpot-free without committing to any particular thermal-model accuracy claim.

3.5.0.3 Wire-delay term.

The floorplanner’s wire term reuses the Bakoglu–Meindl [29] distributed-RC line delay \(\tau(L)=0.69\,RCL^2\) of 3.3, evaluated at the smoothed Manhattan distance \(L_i = \sqrt{(x_{\text{L2}}-x_i)^2+\epsilon^2} + \sqrt{(y_{\text{L2}}-y_i)^2+\epsilon^2} + \ell_{\text{TSV}}\) from each core \(i\) to the L2 macro. The vertical TSV traversal \(\ell_{\text{TSV}}\) is constant within a candidate (since L2 always sits on the opposite tier from the cores in our P1 setup) and the smoothing keeps the term differentiable in \((x_{L2}, y_{L2})\).

3.5.0.4 Objective.

Combining the two pieces yields the analytical floorplanner’s loss, conditioned on a fixed discrete \(z\) chosen by the outer FM enumeration: \[\begin{align} \mathcal{L}(z; x_{L2}, y_{L2}) \;=\; &-\underbrace{\mathrm{IPC}\!\cdot\!f_{\text{sus}}\!\bigl(\hat{T}_{\max}(x_{L2}, y_{L2}; z),\gamma\bigr)}_{\text{BIPS}_2 \text{ proxy (C2 inside obj.)}} \\ &+\, \lambda_{\text{wire}}\!\cdot\!\mathrm{IPC}\!\cdot\!\overline{\tau}(x_{L2}, y_{L2}), \end{align} \label{eq:placer95loss}\tag{14}\] where \(\overline{\tau}\) is the average \(\tau(L_i)\) across cores (in cycles, scaled by \(\mathrm{IPC}\) to share the BIPS unit). We solve 14 with L-BFGS-B subject to the box constraints \((x_{L2},y_{L2})\!\in\![0,W\!-\!w_{\text{L2}}]^2\), multi-started from three initial points (BL corner, die centre, TR corner) for each enumerated \(z\). The global optimum is the best of the \(|\{z\}|\!\times\!3\) candidates. 3 summarises the full procedure.

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3.5.0.5 Validation pass.

The chosen tier assignment \(z^\star\) and continuous optimum \((x_{L2}^\star, y_{L2}^\star)\) define a final layout that is materialised by patching the L2-bearing die’s .flp and reordering the coremem.ptrace columns. One real HotSpot run on this layout supplies the true \(T_{\max}^\star\) that enters 12 (3, lines 11–13). The proxy carries the optimizer through the search; the validation pass guarantees the reported \(\text{BIPS}_2^\star\) uses exactly the same thermal model as every other configuration in the design space.

The analytical floorplanner differs from a wrapper around an existing CAD tool in two ways. First, the closed-form objective is grounded in 12 : \(f_{\text{sus}}\) enters the loss directly, not as a downstream score on a layout that was selected for a different criterion. Second, no thermal simulator is invoked during the optimization itself. The inner loop costs only the proxy evaluation and L-BFGS-B’s gradient queries, both microsecond-scale, so the wall-time per layout is dominated by the single validation HotSpot rather than by repeated solver calls inside the inner loop. The \(\lambda_{\text{wire}}\) coefficient is the only weight in 14 and serves a specific unit-conversion role (cycles to BIPS) rather than balancing competing surrogate objectives in the DAC sense. The wire delay itself is parameter-free at the architectural stage, derived from PTM [30] 45-nm metal RC (\(R{=}50\,\Omega/\text{mm}\), \(C{=}200\,\text{fF}/\text{mm}\) for semi-global wires) via Bakoglu–Meindl.

4 Experimental Results↩︎

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4.1 Experimental Setup↩︎

All experiments run on a Linux workstation with dual Intel Xeon Gold 6426Y CPUs (32 physical cores) and 256 GB RAM. We adopt the 45 nm node parameters from Cool-3D [23] and match McPAT, CACTI, and HotSpot to the same node for consistency across the pipeline.

4.1.0.1 Architectural sweep

We evaluate five workloads on a uniform architectural grid: FFT and CHOLESKY from SPLASH-2 [31] (mixed compute with irregular memory, and sparse Cholesky factorization on the tk14 input, respectively), the McCalpin STREAM [32] memory-bandwidth benchmark, dense matrix multiplication (MATMUL), and a 2D Jacobi five-point stencil (STENCIL). The mix covers compute, bandwidth, sparse, and stencil regimes. The architectural sweep varies L2 size \(\in\{128,\,256,\,512,\,1024,\,2048\}\,\text{kB}\) (CACTI access time spans 6 to 10 cycles at \(f_0\)) and L1D size \(\in\{16,\,32,\,64,\,128\}\,\text{kB}\), giving \(5\times4=20\) architectural configurations per workload and \(5\times20=100\) closed-loop points per cooling envelope. Core count is fixed at four for this study; the 2-tier stack uses pattern P1 (cores on the bottom die, L2 on the top die) with auto die sizing at 70 % utilization. McPAT-derived per-block area is rescaled by a single global calibration factor so that the reference design (4 cores, 32 kB L1D, 512 kB L2 at 45 nm) lands at 150 \(\text{mm}^2\), matching Intel Nehalem-EP minus its L3 region.

4.1.0.2 Cooling envelopes

We evaluate two cooling envelopes with the same package and silicon limits (\(T_{\text{safe}}{=}\SI{95}{\celsius}\) silicon \(T_j^{\max}\), \(T_{\text{amb}}{=}\SI{25}{\celsius}\) data-center inlet, \(f_0{=}\SI{2.0}{\giga\hertz}\), \(f_{\min}{=}\SI{0.4}{\giga\hertz}\), per-config \(\gamma\) from McPAT runtime power):

• Baseline, \(r_{\text{conv}}{=}\SI{3.5}{\kelvin\per\watt}\). Tower heatsink on the package, the nominal operating envelope.

• Stressed, \(r_{\text{conv}}{=}\SI{5.0}{\kelvin\per\watt}\). Reduced cooling headroom, modeling a degraded heatsink such as an aged or partly clogged tower fan, or operation closer to the package thermal limit. This value matches the floorplanner study of 4.4.

Both envelopes use the same \(T_{\text{safe}}\), ambient, and architectural sweep. The two-envelope design tests whether IPC ranks remain stable when sustained frequency moves under tighter heat removal.

4.1.0.3 Per-config pipeline

Each closed-loop point invokes two gem5 passes (front-end for \(\text{IPC}_1\) and back-annotated rerun for \(\text{IPC}_2\) under CACTI-tuned cache latency), one McPAT power pass, one HotSpot steady-state solve at \(f_0\), and one closed-form \(f_{\text{sus}}\) evaluation per 12 . Total simulation volume across the two envelopes is \(200\) completed closed-loop points; the sweep completes in about \(1\) h at 16-way parallelism using per-worker scratch directories to isolate transient files.

4.2 Closed-Form Frequency Validation↩︎

Before reporting rankings built on the closed-form \(f_{\text{sus}}\) of 12 , we confirm that the linearity argument of 3.4 (temperature affine in \(f\) under the uniform-\(\gamma\) assumption 10 ) holds numerically under both cooling envelopes.

We pick four anchor configurations spanning the full thermal regime under the baseline envelope: a cool STREAM point (\(T_{\max}{=}\SI{63.7}{\celsius}\), \(\gamma{=}0.694\)), a borderline-no-throttle MATMUL (\(\SI{93.7}{\celsius}\), \(\gamma{=}0.443\)), an FFT at the throttle boundary (\(\SI{94.6}{\celsius}\), \(\gamma{=}0.444\)), and a heavily throttled FFT (\(\SI{100.0}{\celsius}\), \(\gamma{=}0.446\)). At each anchor we re-run HotSpot at \(f \in \{0.5,1.0,2.0\}\,\si{\giga\hertz}\), scaling the ptrace by \(\gamma{+}(1{-}\gamma)(f/f_0)\). We additionally rerun the STREAM, MATMUL, and heavily throttled FFT anchors under the stressed envelope, where the MATMUL anchor crosses from headroom into throttling and the FFT anchor enters deeper throttling. 3 reports both envelopes, with the per-anchor linearity error \(\Delta_{\text{lin}} = T_{\max}^{\text{HotSpot}}(f) - (T_{\text{amb}} + R_\theta P(f))\) taken across \(f \in \{0.5,1.0,2.0\}\) GHz, and the post-solve safety margin \(\Delta_{\text{safe}} = |T_{\max}^{\text{HotSpot}}(f_{\text{sus}}) - T_{\text{safe}}|\). Rows with \(f_{\text{sus}}{=}f_0{=}\SI{2.0}{\giga\hertz}\) have \(T_{\max}(f_0){<}T_{\text{safe}}\) at the nominal frequency, so no throttling applies and \(T@f_{\text{sus}}\) and \(|\Delta_{\text{safe}}|\) are reported as N/A.

The linearity prediction \(T_{\max}(f){=}T_{\text{amb}}+R_\theta P(f)\) matches the measured HotSpot output to within \(\SI{0.015}{\celsius}\) across all \((4{+}3)\!\times\!3{=}21\) runs, at the level of HotSpot’s Gauss–Seidel convergence tolerance. Under the baseline envelope the heavily throttled FFT anchor solves \(f_{\text{sus}}{=}\SI{1.760}{\giga\hertz}\) and HotSpot drives \(T_{\max}\) to exactly \(T_{\text{safe}}{=}\SI{95.00}{\celsius}\), with \(|\Delta_{\text{safe}}|{=}\SI{0.0}{\celsius}\). Under the stressed envelope the same FFT anchor solves \(f_{\text{sus}}{=}\SI{0.93}{\giga\hertz}\) and the regime-transition MATMUL anchor solves \(f_{\text{sus}}{=}\SI{1.09}{\giga\hertz}\), both landing within \(\SI{0.01}{\celsius}\) of \(T_{\text{safe}}\). The closed-form claim of 3.4 therefore extends to both cooling regimes without modification, and we use it directly in the ranking experiments of the next two subsections.

4.3 Ranking Diagnostic Across Two Cooling Envelopes↩︎

We first quantify how much ranking information an IPC-only evaluator discards under baseline cooling, then repeat the same diagnostic under the stressed envelope to test how the picture changes with cooling headroom. For each of the 100 design points (five workloads at the full 20-config grid each) we record \(\text{IPC}_1\), \(T_{\max}(f_0)\), the closed-form \(f_{\text{sus}}\) from 12 , and the closed-loop \(\text{BIPS}_2{=}\text{IPC}_2\!\cdot\!f_{\text{sus}}\). We compare three rankings: \(\pi_0\) from \(\text{IPC}_1\), \(\pi_1\) from \(\text{IPC}_1\!\cdot\!f_{\text{sus}}\), and \(\pi_2\) from \(\text{BIPS}_2\). 4 reports, per workload, the number of configs \(n\); the throttled fraction (configs with \(T_{\max}{>}T_{\text{safe}}\), equivalently \(f_{\text{sus}}{<}f_0\)); the \(\text{BIPS}_2\)-rank of the IPC-best design (column IPC#1\(\rightarrow\)BIPS\(_2\), ideal value \(1\), range \([1,n]\)); the top-10 overlap \(|\text{Top}_{10}(\pi_0)\cap\text{Top}_{10}(\pi_2)|\); the Kendall-\(\tau\) pair \(\tau_{0,2}\) between \(\pi_0\) and \(\pi_2\) and \(\tau_{1,2}\) between \(\pi_1\) and \(\pi_2\) (the two coincide in this study because no per-method R2 separates them); and the best-config \(\text{BIPS}_2\) ratio of the BIPS-best over the IPC-best design (column “Best gap”, geometric mean across workloads in summary rows).

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Under baseline cooling, 4 reports the per-workload mismatch. Two regimes appear. CHOLESKY, MATMUL, STENCIL, and STREAM retain full thermal headroom across all 20 configs (\(f_{\text{sus}}{=}f_0\) throughout), so \(\pi_0\), \(\pi_1\), and \(\pi_2\) collapse to the same ranking up to a frequency constant. FFT is the only workload with throttled configs (\(75\,\%\)), and accordingly is the one workload where the IPC-best design is not the \(\text{BIPS}_2\)-best: it lands at \(\tau_{0,2}{=}+0.095\) with the IPC-best design at \(\#11\) in \(\text{BIPS}_2\). This baseline result is useful as a control: the corrections do not bind on workloads that retain headroom, but they already bind on FFT, whose power map exceeds the package envelope on the larger-L2 configurations at nominal frequency.

We then re-run the same architectural sweep, layout model, power model, and temperature limit under the stressed envelope (\(r_{\text{conv}}{=}\SI{5.0}{\kelvin\per\watt}\)); the only quantity that changes is the package thermal resistance. Under stressed cooling, the throttle rate rises across all five workloads, and the ranking metrics that were near-trivial under the baseline envelope now diverge.

[tab:ranking95stressed95v4] reports the per-workload metrics in the lower block of the table. The throttle rate climbs from a baseline-envelope mean of \(15\,\%\) to \(68\,\%\) under stressed cooling, with two workloads (CHOLESKY, FFT) at \(100\,\%\) and only STREAM remaining mostly in the headroom regime (\(20\,\%\)). On the throttled side the ranking metrics now diverge: CHOLESKY collapses to \(\tau_{0,2}{=}-0.358\) with the IPC-best design ranking \(\#17\) in \(\text{BIPS}_2\) and a top-10 overlap of \(2/10\); FFT lands at \(\tau_{0,2}{=}+0.105\) with the IPC-best design at \(\#16\). CHOLESKY has \(\tau_{0,2}{<}0\) outright, meaning that picking by IPC\(_1\) ranks designs strictly worse than a uniform random permutation. Across the five workloads the geometric-mean best-config \(\text{BIPS}_2\) gap of IPC-only selection is \(1.07\times\) with the largest individual workload at \(1.12\times\) (MATMUL).

The qualitative picture is consistent across the two envelopes. When sustained frequency does not move (baseline), IPC is a serviceable proxy for BIPS. When sustained frequency moves with the architectural choice (stressed), IPC and BIPS diverge, and the divergence carries the full weight of the post-correction structure \(\text{BIPS}_2{=}\text{IPC}_2\!\cdot\!f_{\text{sus}}\), where both factors are configuration-dependent. The stressed envelope is therefore best read as a reduced-headroom test rather than a more realistic baseline, and the result supports two interpretations. In any deployment that runs near the package thermal limit (degraded cooling, high ambient, sustained AVX or vector loads), the IPC-only ranking is no longer aligned with what silicon delivers. Even in deployments that operate well under \(T_{\text{safe}}\) on average, the BIPS-best architecture under the worst-case cooling differs from the IPC-best, and a designer who picks at the IPC stage forecloses on options that would have won under the binding constraint. Either reading points to the same engineering implication: the two corrections need to be applied before the architecture commitment, not after.

4.4 Layout Co-Design Using the Closed-Form Frequency↩︎

The architectural sweep above evaluates each design with a fixed shelf-pack layout. The layout choice is itself a degree of freedom, and the same closed-form \(f_{\text{sus}}\) that drives the ranking experiments above can serve as the thermal term inside an analytical floorplanner objective. We run four floorplanners on the stressed-cooling sweep over the four workloads (FFT, MATMUL, STENCIL, STREAM) that complete the gem5 R2 back-annotation pipeline at the full L2\(\times\)L1D grid, \(4\times20=80\) configurations in total: the deterministic shelf-pack baseline (cores on the bottom tier, L2 at the bottom-left corner), the cool3d-canonical layout, an SA-plus-\(\lambda\)-mix grid search that reproduces the prior 3D-IC thermal-aware floorplanning template, and the CLIP-3D analytical floorplanner of 3. The ranking diagnostic of [subsec:ranking95stressed] additionally covers CHOLESKY using \(\text{IPC}_1\), which is layout-invariant; the layout-side experiment in this subsection is restricted to the four R2-complete workloads. Each method emits a layout, then a single HotSpot pass yields the realized \(T_{\max}\) and the closed-form throttled clock \(f_{\text{sus}}\) from 12 .

The closed-loop BIPS depends on both the throttled clock and the IPC delivered under the layout’s wire and TSV penalty. The ranking diagnostic above uses \(\text{BIPS}_2{=}\text{IPC}_1\!\cdot\!f_{\text{sus}}\) with \(\text{IPC}_1\) held constant across methods, since gem5 R1 runs before any layout choice. To verify that the layout-conditional IPC also moves in the same direction we re-run gem5 with each method’s optimized wire and TSV cycle counts back-annotated into the cache latency. The realized score is then \(\text{BIPS}_{\text{real}}{=}\text{IPC}_{\text{R2}}\!\cdot\!f_{\text{sus}}\).

5 summarizes the realized BIPS gap over shelf-pack across the 80-configuration sweep, broken down by workload and regime. CLIP-3D wins on every thermally-binding configuration with mean \(\Delta\text{BIPS}_{\text{real}}{=}{+}13.75\,\%\) and max \({+}24.77\,\%\) (FFT at \(L_2{=}128\) kB). On the headroom subset, where the shelf-pack layout does not throttle and the closed-form \(f_{\text{sus}}{=}f_0\) collapses the thermal term, the wire term in the floorplanner objective still pulls L2 closer to the cores. Realized IPC therefore rises and CLIP-3D delivers a mean \(\Delta\text{BIPS}_{\text{real}}{=}{+}5.82\,\%\) even in the headroom regime, with a maximum of \(79.0\,\%\) on a STREAM configuration whose shelf-pack placed L2 at the worst-case wire distance. The conservative \(\text{IPC}_1\) scoring used in the ranking diagnostic undersold this gain because \(\text{IPC}_1\) is layout-invariant by construction.

6 compares all three thermal-aware floorplanners on the same sweep against shelf-pack. Cool3d-canonical and SA + \(\lambda\)-mix both reach essentially the same realized BIPS plateau (\({+}10.59\,\%\) and \({+}10.01\,\%\) on average), but pay \(2.0\times\) and \(2.9\times\) more wall time per configuration than CLIP-3D. The reason is that those methods evaluate three HotSpot candidates each (top-\(K\) winners of an 11-point \(\lambda\)-grid surrogate search), while CLIP-3D pays one HotSpot validation. The closed-form \(f_{\text{sus}}\) inside the CLIP-3D objective predicts \(T_{\max}\) at the optimum well enough that a single confirmation suffices. CLIP-3D therefore sits on the Pareto frontier of the (wall, realized BIPS) plane: the same wall as the deterministic shelf-pack and the same realized BIPS as the surrogate methods.

7 quantifies the gap between the conservative paper formula and the realized BIPS for CLIP-3D. The paper formula reports \({+}2.52\,\%\) mean because \(\text{IPC}_1\) is held fixed across methods. Once each method’s wire and TSV penalty is back-annotated into the cache latency, the realized gap widens to \({+}10.58\,\%\). The mismatch is sharpest in the headroom bucket: the paper formula scores \(0/32\) wins because \(\text{IPC}_1\) is layout-invariant and \(f_{\text{sus}}{=}f_0\) for every non-throttled config, so paper-BIPS is identical across methods, while R2 back-annotation exposes the wire-driven gain as \(26/32\). The paper formula is therefore a conservative pre-verification estimate, while the realized number is the simulator-backed estimate after layout-dependent cache and wire latency are applied.

The realized gap is wider than the paper formula predicts for a concrete reason. \(\text{IPC}_1\) uses gem5’s default cache latency, fixed at the architecture stage and independent of layout, while \(\text{IPC}_{\text{R2}}\) uses the CACTI base latency plus the integer wire and TSV cycles derived from the chosen layout, so a tighter layout (shorter average core-to-L2 wire) reduces effective L2 hit time and lifts IPC. The shelf-pack baseline places L2 in the bottom-left corner, the worst-case wire-distance configuration, so any layout that moves L2 closer to the core cluster pays this penalty back. CLIP-3D’s L-BFGS-B inner loop optimizes the average wire term in addition to the closed-form \(f_{\text{sus}}\) term, which is why it picks up wire-driven IPC even when the configuration is not thermally binding. These two mechanisms (\(f_{\text{sus}}\) gain and wire optimization) split differently across workloads, and 5 resolves them per workload. Throttled rows are dominated by the \(f_{\text{sus}}\) gain, with FFT the largest at mean \(19.7\,\%\) and max \(24.8\,\%\). Headroom rows are smaller and dominated by the wire-term contribution; STREAM at \({+}7.4\,\%\) headroom mean comes entirely from wire optimization since \(f_{\text{sus}}{=}f_0\) collapses the thermal term, and the \(79.0\,\%\) outlier comes from one configuration whose shelf-pack placed L2 at the worst-case wire distance.

Taken together, the ranking diagnostic of 4.3 and the layout co-design above answer two complementary questions on the same physics-aware pipeline. The ranking diagnostic shows that IPC-only selection fails when architectural choices change both instruction throughput and sustainable frequency, with the failure growing as cooling headroom shrinks. The layout co-design shows that the same closed-form \(f_{\text{sus}}\) that diagnoses this failure also drives a single-shot floorplanner that matches surrogate-search BIPS at one-third the wall time. The corrections are not bolted on after the fact; they are the architecture-to-physical lifting itself.

5 Conclusion↩︎

We presented CLIP-3D, an architecture-to-physical lifting pipeline coupled with an analytical 3D thermal-aware floorplanner whose objective embeds a closed-form sustained-frequency expression in place of the HPWL-plus-temperature linear surrogate that prior 3D thermal-aware floorplanners optimize. Across an 80-configuration sweep under stressed cooling, the floorplanner lies on the wall-time vs.realized \(\text{BIPS}_2\) Pareto frontier against shelf-pack, cool3d-canonical, and an SA \(+\,\lambda\)-mix HPWL/\(T_{\max}\) surrogate baseline analogous to recent SA-based 3D thermal-aware floorplanners.

Acknowledgment↩︎

This work was conducted in the JC STEM Lab of Intelligent Design Automation, funded by The Hong Kong Jockey Club Charities Trust. This work was supported in part by the Research Grants Council of the Hong Kong Special Administrative Region, China, under Grant Nos.CUHK14211324 and CUHK7010840, and in part by ACCESS – AI Chip Center for Emerging Smart Systems, supported by the InnoHK initiative of the Innovation and Technology Commission of the Hong Kong Special Administrative Region Government. AI assistants were used for language polishing and partial code generation under the authors’ supervision. All research decisions and technical contributions were made by the authors.

References↩︎