1 Introduction↩︎

The growing demand for heterogeneous, high-performance computing has propelled 2.5D chiplet integration to the forefront of advanced packaging [1]. By assembling pre-verified chiplets on a silicon interposer, 2.5D systems deliver superior performance and design reusability at a fraction of the monolithic development cost [2]. However, the physical placement of chiplets on the interposer is a multi-faceted optimization problem that must simultaneously address wirelength and peak temperature [3].

A diverse set of methodologies has been proposed to tackle this challenge, including simulated annealing [4], [5], sequence-pair-based methods [6], analytical formulations [7], [8], and reinforcement learning [9], [10]. Despite their diversity in optimization strategy, these methods share a common and fundamental limitation in that they all require a pre-defined interposer footprint as input.

This requirement creates a circular dependency in the design flow. The optimal footprint cannot be known without first solving the placement, while the placement itself is constrained by the given dimensions. As shown in Figure 1, an undersized interposer may exclude feasible placements, while an oversized one yields unnecessarily sparse solutions. In practice, designers resort to manual trial-and-error or coarse parameter sweeps over canvas sizes, neither of which can efficiently explore the joint space of interposer dimensions and chiplet configurations. We advocate a paradigm shift in which the interposer footprint becomes an output of the placement optimization rather than an input.

Moreover, even when footprint area is minimized on an oversized interposer, an equally important geometric property neglected by all prior works, is the aspect ratio (AR) of the interposer. In practice, industry standard 2.5D packages almost universally adopt near-square interposer form factors [11]. Furthermore, large area interposers are known to suffer from warpage due to CTE mismatch [12], which an elongated geometry may exacerbate along its longer axis. However, minimizing area alone does not control the layout shape and may yield impractical geometries with extreme aspect ratios.

To jointly address these challenges, we propose FAPlace, a footprint aware mask guided sequential placement framework for 2.5D systems. FAPlace operates on a sufficiently large canvas and employs a novel footprint mask that fuses area compactness with an aspect ratio penalty into a unified spatial cost map. This mask simultaneously drives chiplets toward tight packing and steers the bounding box geometry toward a target shape. Integrated with wirelength and thermal masks, FAPlace delivers holistic multi-physics optimization in a deterministic, single pass procedure.

The specific contributions of this work are:

• We introduce FAPlace, which eliminates the circular dependency by allowing the optimal interposer footprint to emerge as an output of the optimization rather than a pre-defined input.

• We are the first to incorporate interposer aspect ratio as an explicit optimization objective in 2.5D chiplet placement.

• We propose the footprint mask, a unified spatial cost map that jointly minimizes footprint area and penalizes aspect ratio deviation, enabling simultaneous area compactness and shape compliance.

• Experiments demonstrate that FAPlace reduces wirelength and footprint area while achieving near-unity aspect ratios, without compromising thermal performance.

2 Problem Formulation↩︎

Given a set of chiplets \(\mathcal{C} = \{c_1, \dots, c_N\}\), where each chiplet \(c_i\) is characterized by its width \(w_i\), height \(h_i\), and thermal design power \(p_i\), along with a netlist \(\mathcal{N}\) encoding the logical connectivity and a set of pin clumps \(\mathcal{K}\), the goal is to determine placement coordinates \(\mathcal{X} = \{(x_i, y_i)\}_{i=1}^{N}\) and orientations \(\Theta = \{\theta_i\}_{i=1}^{N}\), \(\theta_i \in \{0^\circ, 90^\circ\}\), that jointly optimize the following objectives.

Wirelength. Adopting the flow-based formulation of [4], we define a variable set \(\mathcal{F}\) where \(f^n_{iljk}\) quantifies the connections of net \(n\) routed from pin clump \(l\) on chiplet \(i\) to pin clump \(k\) on chiplet \(j\). The total wirelength is computed as \[WL(\mathcal{X}, \mathcal{F}) = \sum_{i,j \in \mathcal{C}} \sum_{l,k \in \mathcal{K}} \sum_{n \in \mathcal{N}} d_{iljk}(\mathcal{X}) \cdot f^n_{iljk},\] where \(d_{iljk}\) is the Manhattan distance between the corresponding pin clumps.

Peak Temperature. Let \(T(\mathcal{X}, \mathcal{P})\) be the steady-state thermal distribution under placement \(\mathcal{X}\) and power profile \(\mathcal{P}\). The thermal objective minimizes the peak temperature \[T_p(\mathcal{X}) = \max \big( T(\mathcal{X}, \mathcal{P}) \big).\]

Interposer Footprint. Distinct from prior formulations that ignore the footprint, we define a composite footprint objective that captures both the footprint area and the aspect ratio. Specifically, the footprint area is \[A(\mathcal{X}) = W_{bb} \times H_{bb},\] where \(W_{bb}\) and \(H_{bb}\) denote the bounding box width and height. The aspect ratio is defined as \[AR(\mathcal{X}) = \max\!\left(\frac{W_{bb}}{H_{bb}},\; \frac{H_{bb}}{W_{bb}}\right).\] The goal is to minimize footprint area while keeping \(AR\) close to a target value \(AR_{\text{tgt}}\) (e.g., \(AR_{\text{tgt}} = 1\) for a square). The concrete realization of this bi-objective as a unified spatial cost map is detailed in Section 3.3.

3 The FAPlace Framework↩︎

FAPlace is a sequential, mask guided placement framework that determines chiplet locations sequentially on a sufficiently large canvas. As illustrated in Fig. 2, the framework consists of five components: (1) a connectivity-driven ordering strategy, (2) a multi-mask guidance system featuring the novel footprint mask, (3) a unified mask synthesis with greedy selection, (4) footprint extraction, and (5) an adaptive thermal-spacing mechanism to satisfy thermal constraints.

3.1 Placement on a Large Canvas↩︎

Unlike conventional methods that confine placement within a pre-specified interposer boundary, FAPlace initializes on a deliberately oversized canvas. The rationale is twofold: first, a large canvas eliminates the infeasibility issues caused by an undersized interposer; second, it decouples the placement quality from the canvas specification, allowing the actual footprint to be determined entirely by the mask-guided optimization. After all chiplets are placed, the layout is shrunk to a tight bounding box and thermally re-evaluated under the compact dimensions. The canvas discretization follows a uniform \(G \times G\) grid, and \(2G^2\) candidate locations are evaluated at each step to account for both standard and \(90^\circ\)-rotated orientations.

3.2 Connectivity-Driven Ordering↩︎

We employ a connectivity-driven strategy: the chiplet with the largest area is selected as the seed. Subsequently, at each iteration, the unplaced chiplet with the strongest total connection to the already-placed set is selected: \[c_{\text{nx}} = \mathop{\arg\max}\limits_{c_i \in \mathcal{C}_{\text{upl}}} \sum_{c_j \in \mathcal{C}_{\text{pl}}} \lambda_{ij},\] where \(\lambda_{ij}\) is the connection weight between chiplets \(c_i\) and \(c_j\), \(\mathcal{C}_{\text{pl}}\) and \(\mathcal{C}_{\text{upl}}\) are the placed and unplaced sets, respectively. Ties are broken by selecting the candidate with the larger area.

3.3 Footprint Mask↩︎

The footprint mask is the central technical contribution of this work. It encodes a spatial inductive bias that jointly drives chiplets toward compact configurations with a well-proportioned bounding box. For each candidate grid cell \((i,j)\), the mask evaluates the geometric consequence of placing the next chiplet \(c_{\text{nx}}\) at that location.

3.3.1 Area Cost↩︎

Let \(A_{\text{curr}}\) denote the bounding box area of the already placed chiplets. When \(c_{\text{nx}}\) is centered at \((i,j)\), the new bounding box becomes: \[\begin{align} W_{\text{new}}(i,j) &= \max(x_{\max}, i+\tfrac{w_{\text{nx}}}{2}) - \min(x_{\min}, i-\tfrac{w_{\text{nx}}}{2}), \\ H_{\text{new}}(i,j) &= \max(y_{\max}, j+\tfrac{h_{\text{nx}}}{2}) - \min(y_{\min}, j-\tfrac{h_{\text{nx}}}{2}), \end{align} \label{eq:bb}\tag{1}\] where \((x_{\min}, x_{\max}, y_{\min}, y_{\max})\) are the current bounding box extremes. The normalized area expansion cost is: \[R_A(i,j) = \frac{W_{\text{new}} \cdot H_{\text{new}} - A_{\text{curr}}}{w_{\text{nx}} \cdot h_{\text{nx}}}. \label{eq:area95cost}\tag{2}\]

3.3.2 Aspect Ratio Penalty↩︎

The AR penalty quantifies how much the prospective bounding box deviates from the target shape: \[R_{AR}(i,j) = \left( \max\!\left(\frac{W_{\text{new}}}{H_{\text{new}}},\; \frac{H_{\text{new}}}{W_{\text{new}}}\right) - AR_{\text{tgt}} \right)^{\!2}. \label{eq:ar95cost}\tag{3}\] The quadratic form imposes a mild penalty near the target and an increasingly severe one for extreme deviations, reflecting the practical impact of AR on manufacturability.

3.3.3 Mask Fusion↩︎

Both cost components are independently normalized to \([0,1]\) and fused into the footprint mask: \[\mathcal{M}_{F}(i,j) = (1-\eta) \cdot \hat{R}_A(i,j) + \eta \cdot \hat{R}_{AR}(i,j), \label{eq:shape95mask}\tag{4}\] where \(\hat{\cdot}\) denotes min-max normalization and spatial bias weight \(\eta \in [0,1]\) controls the trade-off between area compactness and AR compliance.

3.4 Wire Mask and Thermal Mask↩︎

To guide wirelength and thermal optimization, FAPlace employs two additional masks, inspired by Maskplace [13].

3.4.1 Wire Mask↩︎

For the next chiplet \(c_{\text{nx}}\), the Wire Mask approximates the routing cost at each candidate location based on the Manhattan distance to connected, already placed chiplets: \[\mathcal{M}_{WL}(i,j) = \sum_{c_k \in \mathcal{C}_{\text{pl}}} \lambda(c_{\text{nx}}, c_k) \cdot \left( |i - x_k| + |j - y_k| \right),\] where \((x_k, y_k)\) are the coordinates of placed chiplet \(c_k\) and \(\lambda(\cdot,\cdot)\) denotes the connection weight.

3.4.2 Thermal Mask↩︎

For high-power chiplets (those exceeding a power threshold \(p_{\text{th}}\)), the Thermal Mask leverages the steady-state temperature distribution \(T(\mathcal{X}, \mathcal{P})\) computed by HotSpot [14] for the currently placed chiplets: \[\mathcal{M}_T(i,j) = \begin{cases} T(i,j), & \text{if } p(c_{\text{nx}}) > p_{\text{th}} \\ 0, & \text{otherwise} \end{cases}\] This selectively activates thermal guidance only when placing high power chiplets, avoiding unnecessary constraints on low-power ones.

3.5 Unified Mask and Greedy Selection↩︎

The individual masks are normalized and synthesized into a Unified Mask: \[\mathcal{M}_{\text{uni}} = (1-\beta)\cdot\alpha \cdot \hat{\mathcal{M}}_{WL} + \beta \cdot \hat{\mathcal{M}}_{T} + (1-\beta)\cdot\gamma \cdot \hat{\mathcal{M}}_{F}, \label{eq:unified}\tag{5}\] where \(\alpha = \gamma=0.5\).

To ensure physical validity, a Position Mask \(\mathcal{M}_{\text{pos}}\) is applied to filter out infeasible locations, including overlaps or boundary violations: \[\mathcal{M}_{\text{pos}}(i,j) = \begin{cases} 0, & \text{if } (i,j) \in \Omega \\ +\infty, & \text{otherwise} \end{cases}\] where \(\Omega\) is the set of feasible positions. The greedy selection then identifies the globally optimal position and orientation: \[(x_t^*, \theta_t^*) = \mathop{\arg\min}_{x_t,\; \theta \in \{0^\circ, 90^\circ\}} \left( \mathcal{M}_{\text{uni}}(x_t, \theta) + \mathcal{M}_{\text{pos}}(x_t, \theta) \right).\] This deterministic, single pass procedure places all \(N\) chiplets in exactly \(N\) steps.

3.6 Footprint Extraction↩︎

Once all chiplets have been placed on the sufficiently large canvas, the interposer footprint is extracted and the layout is thermally evaluated under realistic dimensions.

After the last chiplet \(c_N\) is placed, the final bounding box dimensions \(W_{\text{new}}\) and \(H_{\text{new}}\) are obtained following Eq. 1 . The interposer size is then set to \[L_{\text{intp}} = \left\lceil \frac{\max(W_{\text{new}},\; H_{\text{new}})}{g} \right\rceil \cdot g,\] where \(g\) is the grid granularity and the ceiling operation ensures alignment with the discretization. All chiplet coordinates are shifted to re-center the layout within this compact \(L_{\text{intp}} \times L_{\text{intp}}\) region. This step converts the placement on the oversized canvas into a concrete, fabrication-ready interposer specification.

3.7 Adaptive Thermal-Spacing↩︎

To guarantee compliance with a peak temperature limit \(T_{\text{limit}}\), FAPlace employs an adaptive thermal-spacing (ATS) mechanism. ATS treats the thermal weight \(\beta\) as a tunable parameter and wraps around the placement and tight canvas evaluation pipeline: at each iteration, the full sequential placement is executed with the current \(\beta\), followed by footprint extraction. A binary search is then performed to identify the minimum \(\beta^*\) that satisfies the constraint: \[\beta^* = \min \left\{ \beta \in [0, 1] \;\middle|\; T_p(\beta) \le T_{\text{limit}} \right\}.\] A lower \(\beta\) prioritizes compact placement at the expense of higher temperature; ATS efficiently identifies the tightest packing that remains thermally safe.

4 Experiments↩︎

4.1 Experimental Setup↩︎

We evaluate FAPlace on a benchmark suite comprising two real-world industry architectures, MultiGPU [4] (Sys 1) and CPU-DRAM [15] (Sys 2), along with three additional synthetic systems of increasing complexity, as summarized in Table 1. We compare against TAP-2.5D [4], a representative SA-based thermal-aware placement method.

Wirelength is computed using a multi-commodity flow formulation solved via MILP with IBM ILOG CPLEX v12.8. Peak temperature is obtained from HotSpot v6.0 [14]. All metrics, including wirelength, peak temperature, footprint area, and AR, are reported on the tight bounding box canvas after footprint extraction.

FAPlace operates on a sufficiently large canvas without any footprint specification, and the interposer footprint emerges as an output. For baseline methods that require a pre-defined canvas, we use the interposer size produced by FAPlace. This represents a favorable setting for the baselines, as they are given a near-optimal canvas derived from FAPlace’s own optimization.

The target AR is set to \(AR_{\text{tgt}} = 1.0\) (square). The spatial bias weight \(\eta = 0.4\) for Sys 1 and \(\eta = 0.2\) for the rest of designs.

4.2 Main Results↩︎

We exclude other prior methods from comparison as their implementations are not publicly available. Table ¿tbl:tab:comparison? presents the comparison between TAP-2.5D and FAPlace. Recall that TAP-2.5D is given FAPlace’s output footprint as its input canvas, representing a favorable scenario for the baseline. Despite this advantage, FAPlace achieves superior results across all key metrics. FAPlace reduces wirelength by approximately \(2\times\) on average across all benchmarks, with particularly pronounced improvements on Sys 3 and Sys 5. Both methods achieve comparable thermal profiles, with TAP-2.5D averaging only \(1.02\times\) higher peak temperature, confirming that FAPlace’s compact placements do not sacrifice thermal quality. Meanwhile, FAPlace is approximately \(4\times\) faster than TAP-2.5D, as its deterministic single pass mask-guided greedy selection avoids the iterative stochastic search inherent to SA.

Figure [fig:canvas] visualizes the thermal layouts for Sys 2 and Sys 5. While TAP-2.5D suffers from localized heating due to clustered or uniformly scattered placements, FAPlace strategically separates heat sources. FAPlace effectively mitigates peak temperatures and facilitates heat dissipation across the interposer.

4.3 Evaluation on a Large Canvas↩︎

The main comparison in Table ¿tbl:tab:comparison? provides TAP-2.5D with FAPlace’s optimized \(L_{\text{intp}}\) as its input canvas, effectively supplying a geometric prior that removes the need for TAP-2.5D to determine the interposer footprint on its own. To eliminate this advantage and establish a level playing field, we run TAP-2.5D on the same sufficiently large canvas used by FAPlace, using Sys 1 as a case study. For a fair comparison, we select a TAP-2.5D placement whose peak temperature closely matches that of FAPlace, ensuring that differences in wirelength, bounding box area, and aspect ratio are not artifacts of differing thermal budgets.

As shown in Table 2, without the geometric prior, TAP-2.5D exhibits significant degradation across all metrics. These results demonstrate that TAP-2.5D relies heavily on a well-specified interposer footprint to produce compact, well-proportioned placements. In contrast, FAPlace, guided by the footprint mask, autonomously converges to a tight and near-square layout without requiring any pre-defined boundary specification.

4.4 Ablation Study↩︎

Table 3 shows the effect of the footprint mask. Without it, the placement can still achieve comparable wirelength and peak temperature, yet the overall layout quality degrades significantly. Specifically, the average aspect ratio increases by 1.80\(\times\), and the interposer side length grows by 1.40\(\times\). This demonstrates that the footprint mask serves as an effective shape constraint without compromising electrical or thermal performance.

The necessity of both mask components is further highlighted by specific design cases. On Sys 1, removing the mask actually yields a smaller bounding box area, yet the aspect ratio surges from 1.12 to 3.07. This elongation forces the layout onto an 85 mm interposer instead of a 56 mm one. Such an elongated shape cannot be efficiently accommodated on a square interposer, entirely negating the apparent area savings. Conversely, on Sys 2, although the aspect ratio remains unaffected without the mask, the bounding box area nearly doubles from 15 to 28 cm\(^2\), expanding the required interposer from 43 mm to 58 mm. These cases illustrate that both the area cost and the aspect ratio penalty are essential for the footprint mask to enforce a compact and manufacturable outline.

4.5 Impact of Area Cost and AR Penalty↩︎

We conduct a sensitivity analysis to examine the individual contributions of the area cost and AR penalty within the footprint mask. Specifically, we vary the weighting coefficient \(\eta\) and report the resulting bounding box area and aspect ratio on Sys 1 in Figure 5. Figure 6 shows the corresponding layout visualizations. When the AR penalty is entirely disabled (\(\eta = 0\)), the placement is driven predominantly by bounding box area optimization. Although this configuration achieves the absolute minimum bounding box area, it results in an extreme aspect ratio of approximately 4.5. Visually, this manifests as an elongated, quasi-one-dimensional chain of chiplets, which is highly impractical for real-world manufacturing. As \(\eta\) increases, the AR penalty effectively regularizes the layout geometry. We observe a sharp decline in the AR, which converges to the target value of approximately 1.0 (i.e., a square footprint) once \(\eta \ge 0.4\).

4.6 Impact of Adaptive Thermal-Spacing↩︎

To validate the responsiveness of the ATS mechanism, we tracked both the performance in Figure 7 and the corresponding spatial layout in Figure 8 during the placement of Sys 2, targeting a peak temperature limit of 96\(^\circ\mathrm{C}\). Driven by the ATS, the layout dynamically evolves to resolve thermal violations. Initially, a low thermal weight forces a dense core, which minimizes wirelength but causes a severe thermal violation. As ATS dynamically increases thermal weight to penalize localized heating, the layout expands, dropping the temperature to 100\(^\circ\mathrm{C}\) at the expense of increased wirelength. By Epoch 3, ATS converges on the optimal weight. The layout transforms into a dispersed, U-shaped perimeter configuration, successfully satisfying the rigorous 96\(^\circ\mathrm{C}\) limit while establishing the minimal acceptable wirelength for this specific thermal constraint.

5 Conclusion↩︎

In this paper, we presented FAPlace, a footprint-aware mask-guided sequential placement framework that eliminates the circular dependency between chiplet placement and interposer footprint specification in 2.5D systems. By operating on a sufficiently large canvas and introducing a novel footprint mask that fuses area compactness with an aspect ratio penalty, FAPlace allows the optimal interposer footprint to emerge naturally as an output of the optimization. Integrated with wirelength and thermal guidance masks, the framework achieves holistic multi-physics optimization through a deterministic, single pass process. Experimental results across diverse benchmarks demonstrate that FAPlace reduces wirelength and footprint area while achieving near-unity aspect ratios, without compromising thermal performance.

References↩︎