Utility-scale quantum algorithms require quantum operations at extremely low error rates that are orders of magnitude lower than state-of-the-art error rates on physical qubits [2]–[4]. Fault-tolerant quantum computation (FTQC) aims to bridge this gap between the desired error rate and physical error rates by encoding logical quantum information into quantum error correction (QEC) codes. The rotated surface code (RSC) is a leading QEC code candidate for experimental implementation, since the RSC has simple stabilizer patterns and a high threshold [5], [6]. However, a marked shortcoming of the RSC is its low qubit efficiencya single patch of distance-\(d\) RSC encodes only one logical qubit with \(d^2\) physical qubits. Recent constructions of quantum low-density parity-check (qLDPC) codes [7], [8], such as bivariate bicycle codes [9]–[11], tile codes [12]–[14], hypergraph product codes [15], [16], and lifted product codes [17], [18], offer significantly higher encoding efficiency than the RSC. Direct implementations of qLDPC codes generally require non-local couplings in each round of syndrome extraction (SE), with the required coupling range depending on the specific code construction.

Reconfigurable neutral atom arrays, a rapidly evolving quantum platform supporting long-range connectivity [19]–[21], are promising for realizing these qLDPC codes. Nevertheless, long-range gates, implemented via atom shuttling, can introduce additional physical errors and implementation complexity [19], [20]. Thus, an important consideration is to reduce qubit overhead while limiting the use of long-range gates. For instance, measuring only a fraction of stabilizer generators in each SE round is an effective approach to mitigate the cost of long-range connectivity for implementing qLDPC codes [22]–[24]. A few recent protocols propose using native \(\mathrm{iSWAP}\) gates on superconducting platforms [25]–[27] to extract syndromes and perform routing simultaneously, thereby compiling the code-specific non-local dataancilla connectivity of certain qLDPC codes into SE circuits with only nearest-neighbor coupling [28]–[30]. Alternatively, code concatenationconcatenating a level-1 QEC code on top of a level-0 RSC [1], [31]allows a long time window for measuring non-local level-1 stabilizers, thereby amortizing the demand on non-local connectivity. In particular, a recently proposed quantum memory architecture, yoked surface codes [1], implements specific high-rate level-1 codes on the RSC with only nearest-neighbor connectivity and achieves a three-times higher qubit efficiency compared to the RSC. These recent developments demonstrate promising routes toward high-rate quantum memories under restricted connectivity, while motivating the exploration of logical operations under similar hardware constraints.

In this work, we propose a new FTQC architecture, the hierarchical logical processor (HLP), which implements a high-rate quantum CSS code concatenated with the RSC. HLPs, based on light-weight ancilla patches and transversal CNOT gates, can combine high encoding efficiency with infrequent use of long-range gates and support parallel logical measurements. The key mechanism underlying HLPs is a type of transversal CNOT gate, called the hybrid-unit CNOT gate, that couples an elongated RSC patch (a shuttle bus) to multiple RSC patches (cores) simultaneously. In HLPs, cores and shuttle buses function as level-1 data and ancilla qubits, respectively. We design transversal-CNOT-based readout gadgets, capable of measuring long level-1 Pauli \(\mathsf{X}\) or \(\mathsf{Z}\) operators using only a single shuttle bus. By concurrently using multiple readout gadgets, we can perform level-1 SE substantially faster and with smaller qubit overhead compared with yoked surface codes [1]. We validate our constructions by both theoretical analysis and circuit-level simulations.

Extending beyond logical memory, we propose logical measurement sequences, each composed of a series of readout gadgets, to reliably measure logical Pauli \(X\) or \(Z\) operators. Readout gadgets from different logical measurement sequences can be densely packed to allow parallel measurements of multiple logical operators at the cost of increased use of shuttle buses and non-local transversal CNOT gates. We prove that this protocol achieves full level-1 distance and benchmark it with circuit-level simulations. Additionally, we propose two extension modules that can further enhance the logical functionality of HLPs. First, we propose \(H\)-transformed and \(HS\)-transformed readout gadgets for general logical Pauli measurements. Second, we extend the hybrid-unit CNOT gates to enable joint measurements of logical operators on an HLP and external RSC patches. With relaxed requirements on long-range connectivity, beyond-RSC encoding efficiency, and parallel logical measurement capability, the HLP provides a promising building block for large-scale FTQC architectures.

Consider an HLP implementing a distance-\(d_{1}\) level-1 CSS code \(\mathcal{C}_1\) concatenated with the distance-\(d_{0}\) RSC (the level-0 code). The HLP is supported on two types of working units: cores and shuttle buses (Fig. 1 (a)). Each core is a distance-\(d_{0}\) RSC patch, serving as a level-1 data qubit for \(\mathcal{C}_1\); each shuttle bus is an elongated RSC patch of width \(d_{0}\) and length \(d_{0}d_{1}\). A shuttle bus whose logical \(X\) (or \(Z\)) operator runs along the long edge is called an \(X\) (or \(Z\)) bus. We can perform a transversal CNOT gate with a single \(X\) bus on the control side and up to \(d_{1}\) cores on the target side (Fig. 1 (b)). Similarly, we can perform a transversal CNOT gate with up to \(d_{1}\) cores on the control side and a single \(Z\) bus on the target side (Fig. 1 (c)). We refer to the first and the second types of transversal CNOT gates as bus-core and core-bus CNOT gates, respectively. We refer to them collectively as hybrid-unit CNOT gates. With an \(X\) (or \(Z\)) bus as a level-1 ancilla qubit, an \(X\)-basis (or Z-basis) readout gadget can measure a level-1 Pauli \(X\) (or \(Z\)) operator using core-bus (or bus-core) CNOT gates as shown in Fig. 1 (de). We perform level-1 SE on an HLP by extracting level-1 stabilizers with these readout gadgets.

We first consider basic requirements on readout gadgets and their arrangements for running level-1 SE. For every \(X\)-basis readout gadget, \(X\) errors on the \(X\) bus can propagate to multiple cores through bus-core CNOT gates, thereby inducing correlated errors on cores, which would deteriorate the performance of level-1 SE. We note that an \(X\) bus with an \(X\)-basis distance of \(d_{0}d_1\) already strongly suppresses logical \(X\) errors on the bus, which directly induce level-1 hook errors on cores. We insert at least \(\alpha_{\mathsf{b}}d_{0}\) level-0 SE rounds on the \(X\) bus between its initialization (or measurement) and the first (or last) core-bus CNOT gate, and at least \(\alpha_{\mathsf{b}}d_{0}\) level-0 SE rounds between every two adjacent core-bus CNOT gates to limit the propagation speed of \(X\) errors on the bus (Fig. 1). Here, the parameter \(\alpha_{\mathsf{b}}\) depends on \(d_{1}\). Similarly, \(Z\) errors on cores can propagate to multiple \(X\) buses through bus-core CNOT gates, thereby inducing correlated readout errors on these \(X\)-basis readout gadgets. Define the separation between two bus-core CNOT gates as the minimum number of padded level-0 SE rounds between them on every working unit acted on by both of them. Define the separation between two \(X\)-basis readout gadgets as the minimum separation between every pair of bus-core CNOT gates from each gadget. We require every two \(X\)-basis readout gadgets to be separated by at least \(\alpha_{\mathsf{c}}d_{0}\) SE rounds. The same argument applies to \(Z\)-basis gadgets, for which we set the same constraints as above. We refer to \(\alpha_{\mathsf{b}}\) and \(\alpha_{\mathsf{c}}\) as compilation parameters. For simplicity, we restrict to HLPs with perfect time boundaries: all level-0 and level-1 stabilizers are measured perfectly at initialization and final measurement. Thus, cores have perfect time boundaries, whereas shuttle buses are still initialized and measured transversally. We prove (under a phenomenological noise model) that by setting \(\alpha_{\mathsf{b}}=d_{1}\) and \(\alpha_{\mathsf{c}}=1\), we can effectively suppress level-1 error correlations. See the Supplementary Information for the formal theorem statement and proof.

The compilation parameter \(\alpha_{\mathsf{b}}\) characterizes the sparsity of hybrid-unit CNOT gates on every shuttle bus. In other words, a layer of long-range physical CNOT gates is required at most once per \(\alpha_{\mathsf{b}} d_{0}\) level-0 SE rounds for every shuttle bus. Similarly, the compilation parameter \(\alpha_{\mathsf{c}}\) characterizes the sparsity of core-bus (or bus-core) CNOT gates on a core. We can also make a stronger requirement that every two readout gadgets (regardless of their basis) should be separated by at least \(\alpha_{\mathsf{c}}d_{0}\) level-0 SE rounds. (All level-1 SE circuits for our concrete HLP constructions in the following satisfy this constraint.) In this way, long-range CNOT gates are required only once per \(\Theta(d_{0})\) level-0 SE rounds for every working unit. We note that larger compilation parameters relax the demand on long-range connectivity at the cost of longer level-1 SE round time, which serves as the fundamental timescale for logical operations. Thus, we would like to minimize compilation parameters as long as (i) the level-1 \(X\) (or \(Z\)) errors are still effectively uncorrelated, and (ii) the hardware can keep up with the required long-range connectivity.

A Level-1 memory circuit on an HLP is implemented by a level-0 circuit, consisting of level-0 SE on all working units, transversal initialization and measurement on shuttle buses, and hybrid-unit CNOT gates. The level-0 circuit generates level-0 detectors (composed of level-0 stabilizer measurements from at most two adjacent level-0 SE rounds); the level-1 memory circuit generates level-1 detectors corresponding to measurement results of level-1 stabilizers in two adjacent level-1 SE rounds. To decode the level-1 memory circuit, we first perform a matching-based level-0 decoding on level-0 detectors, which amounts to decoding circuits on the RSC (and the elongated RSC) with level-0 SE rounds interleaved by structured transversal CNOT gates [32]–[38]; we then extract soft outputs [39] from segments of the level-0 decoding graphs on cores and shuttle buses, such that each soft output estimates the error probability at the corresponding level-1 error location; finally, we perform level-1 decoding on level-1 detectors, with level-1 error probabilities informed by soft outputs.

We benchmark the memory performance of our HLP design with two types of matchable level-1 codes, the Iceberg code and the 2D parity check code, following Ref. [1]. We refer to the latter as the Square Berg code in the following to avoid confusion with qLDPC codes. We fix \(\alpha_{\mathsf{c}}=1\) in our numerical simulations. We perform circuit-level simulation of (i) an HLP with the \([[4,2,2]]\) Iceberg code as its level-1 code and (ii) an HLP with the \([[64,34,4]]\) Square Berg code (Fig. 2 (a)) as its level-1 code under the circuit-level uniform depolarizing noise model with a physical error rate of \(10^{-3}\). The first HLP extracts the level-1 \(X\) and \(Z\) stabilizers sequentially in a level-1 SE round. We observe that, under both compilation-parameter settings \(\alpha_{\mathsf{b}}=0.5\) and \(\alpha_{\mathsf{b}}=1\), the logical error rate (LER) decays with increasing core distance at nearly twice the rate observed for the RSC. The second HLP on the \([[64,34,4]]\) Square Berg code uses eight concurrent shuttle buses to extract level-1 stabilizers in parallel (Fig. 2 (a)). Its LER decays with increasing core distance at approximately twice the rate observed for the first HLP. These circuit-level simulations indicate that both HLPs operate close to their full distance \(d_{0}d_{1}\). We develop a high-speed heuristic simulator, the soft-output simulator (similar to the gap simulator in Ref. [1]), that directly samples errors and performs decoding at level 1, thereby enabling fast benchmarking of large-scale HLPs. We find close agreement between the soft-output and circuit-level simulation results (Fig. 2 (b)). With the soft-output simulator, we perform level-1 simulation on HLPs with even larger level-1 code sizes and extrapolate their memory performance. We see that with the \([[256,194,4]]\) Square Berg code as the level-1 code, our HLP (now with sixteen concurrent shuttle buses) has a three to four times higher qubit efficiency compared to the RSC over a wide range of target logical error rates, from \(10^{-10}\) to \(10^{-15}\). Compared to the yoked surface code [1] with the same level-1 code and circuit-level noise model, our HLP offers a reduction of 100200 physical qubits in space overhead per logical qubit and a \(20\) \(30\)-fold reduction in level-1 SE round time at similar target logical error rates. See the Supplementary Information for details on circuit-level and soft-out simulations. We note that our HLP on the \([[256,194,4]]\) Square Berg code still has roughly ten times larger level-1 SE round time compared to the RSC baseline set as \(d\) level-0 SE rounds for a distance-\(d\) RSC. This round time sets a lower bound on the latency for logical feedforward operations. However, the logical processing speed also depends on the logical circuit at hand and the parallelism of logical operations. We now show how logical Pauli measurements can be performed in parallel on an HLP.

We use a sequence of \(X\)-basis (or \(Z\)-basis) readout gadgets to reliably measure a logical Pauli \(X\) (or \(Z\)) operator. We call such a sequence a logical measurement sequence (LMS), and call the readout gadgets in an LMS logical readout gadgets. More specifically, an LMS consists of \(d_{1}\) logical readout gadgets embedded in \(d_{1}\) consecutive level-1 SE rounds, such that each level-1 SE round contains exactly one logical readout gadget (Fig. 3 (a)). Every pair of adjacent logical readout gadgets in an LMS generates an additional level-1 detector to check for readout errors on either gadget. We refer to an LMS based on \(X\)-basis (or \(Z\)-basis) logical readout gadgets as an \(X\)-basis (or \(Z\)-basis) LMS. We require each \(X\)-basis (or \(Z\)-basis) logical readout gadget in an \(X\)-basis (or \(Z\)-basis) LMS to be separated by at least \(\alpha_{\mathsf{c}} d_{0}\) level-0 SE rounds from both the other logical readout gadgets in the same LMS and \(X\)-basis (or \(Z\)-basis) readout gadgets for level-1 SE, so as to suppress correlations among readout errors on these gadgets. When it comes to measuring multiple logical Pauli \(X\) or \(Z\) operators, we can perform level-1 decoding for each LMS independently, based on the level-1 detectors from level-1 SE and the level-1 detectors generated by this LMS. Moreover, we do not need to suppress error correlation between readout errors on logical readout gadgets in different LMSs. Therefore, the separation between each pair of logical readout gadgets from two different LMSs can be as small as one level-0 SE round (Fig. 3 (b)). This allows dense packing of logical readout gadgets from different LMSs inside a level-1 SE round, thereby enabling high parallelism in logical operations at the cost of increased use of ancillary shuttle buses and long-range CNOT gates.

We benchmark logical Pauli measurements on an HLP using the \([[8,6,2]]\) Iceberg code as the level-1 code. We label level-1 data qubits of the code by \(\{1,\cdots,8\}\) and logical qubits by \(\{1,\cdots,6\}\). We choose the logical \(Z\) operator for the \(i\)th logical qubit according to \(\overline{\mathsf{Z}}_{i}:=\mathsf{Z}_{i+1}\otimes\mathsf{Z}_{8}\). Consider the following three logical \(Z\) operators \(\mathsf{Z}_2\otimes\mathsf{Z}_{3}\otimes\cdots\otimes\mathsf{Z}_{7}\), equivalently \(\overline{\mathsf{Z}}_{1}\cdot\overline{\mathsf{Z}}_{2}\cdots\overline{\mathsf{Z}}_{6}\); \(\mathsf{Z}_{2}\otimes\mathsf{Z}_{3}\otimes\mathsf{Z}_{4}\otimes\mathsf{Z}_{8}\), equivalently \(\overline{\mathsf{Z}}_1\cdot\overline{\mathsf{Z}}_2\cdot\overline{\mathsf{Z}}_3\); and \(\mathsf{Z}_{5}\otimes\mathsf{Z}_{6}\otimes\mathsf{Z}_7\otimes\mathsf{Z}_8\), equivalently \(\overline{\mathsf{Z}}_4\cdot\overline{\mathsf{Z}}_5\cdot\overline{\mathsf{Z}}_6\). We examine two circuits, both with five level-1 SE rounds and perfect time boundaries. The first circuit uses a single LMS to measure the first logical \(Z\) operator, whereas the second circuit uses three LMSs to measure the three logical \(Z\) operators listed above. Time boundary conditions for logical operators in both circuits guarantee predetermined LMS outcomes and allow logical errors on unmeasured logical degrees of freedom to be detected; see the Supplementary Information for a detailed description. Moreover, for the second circuit, the separation between logical readout gadgets belonging to different LMSs can be as small as one level-0 SE round. We observe that the presence of LMSs does not appreciably increase the total logical error rate, and that the error rates for LMSs are significantly lower than logical memory error rates. These results demonstrate both (i) the feasibility of using an LMS to measure long logical Pauli operators and (ii) the parallelizability of LMSs.

Now consider measuring a general logical operator \(\mathsf{P}_{xz}:=i^{x\cdot z}\mathsf{X}_{1}^{x_1}\mathsf{Z}_1^{z_1}\otimes \cdots\otimes \mathsf{X}_{n_1}^{x_{n_1}}\mathsf{Z}_{n_1}^{z_{n_1}}\), where \(n_1\) is the number of level-1 data qubits; \(x=(x_1,\cdots,x_{n_1})\) and \(z=(z_{1},\cdots,z_{n_1})\) are both elements in \(\mathbb{Z}_2^{n_1}\). If \(x\cdot z=0\), we propose the \(H\)-transformed gadget (Fig. 3 (d)) to measure \(\mathsf{P}_{xz}\). This gadget starts with a \(Z\) bus and performs core-bus CNOT gates according to the \(Z\) component in \(\mathsf{P}_{xz}\), then switches to an \(X\) bus via a transversal \(H\) gate and performs bus-core CNOT gates according to the \(X\) component in \(\mathsf{P}_{xz}\), and finally measures the bus in \(X\) basis. Due to the close resemblance between the first (or second) half of the \(H\) gadget and a \(Z\)-basis (or \(X\)-basis) readout gadget, we can similarly construct LMSs from \(H\)-transformed gadgets, thereby achieving full level-1 distance for measuring \(\mathsf{P}_{xz}\) and parallelizability comparable to that of LMSs based on \(X\)-basis or \(Z\)-basis readout gadgets. For the \(x\cdot z=1\) case, we can also use the \(H\)-transformed gadget to measure \(\mathsf{P}_{xz}\) given an ancillary logical \(Y\) state (which would remain invariant under the measurement) [40]. To remove the need for this catalytic logical \(Y\) state, we propose the \(HS\)-transformed readout gadget in Fig. 3 (e), where the logical \(S\) gate in the gadget can be performed by a mid-cycle fold transversal gate [25], [41]. Finally, the hybrid-unit CNOT gates between shuttle buses and cores with the same width can be straightforwardly extended to act between shuttle buses and external cores (RSC patches) with distance \(d_{ext}\) satisfying \(d_{0}\leq d_{ext}\leq d_{0}d_{1}\) (see Fig. 3 (f)). This allows a shuttle bus to perform joint logical Pauli measurements involving logical qubits hosted on both an HLP and external cores. We leave numerical benchmarking of these protocols for future work.

To summarize, we design the HLP, a concatenation-based FTQC architecture that can offer beyond-RSC encoding efficiency while using long-range CNOT gates as infrequently as once every \(\Theta(d_0)\) level-0 SE rounds for each working unit, where \(d_{0}\) is the base RSC distance. The HLP architecture crucially relies on transversal hybrid-unit CNOT gates between cores (RSC patches) and shuttle buses (elongated RSC patches). Leveraging these hybrid-unit CNOT gates, we design readout gadgets to perform level-1 SE and LMSs to perform logical measurements in parallel. These protocols and our numerical benchmarking serve as a starting point for using HLPs in large-scale FTQC. There is a broad range of directions for future investigation. First, we expect that the memory overhead can be further lowered by using level-1 codes with higher rates and slightly larger level-1 distances compared to the Square Berg code used here. One may also consider changing the level-0 code from the RSC to a small qLDPC code and redesigning shuttle buses for it. Recent works on logical operations [42]–[52] and soft-information decoding [53]–[56] for qLDPC codes can help in this new design. In this way, we may obtain a logical memory architecture achieving utility-scale logical error rates at an encoding rate close to a small qLDPC code with moderate use of long-range connectivitylong-range connectivity for a level-0 SE round should be at the same scale as the small qLDPC code, and long-range connectivity for level-1 SE should be amortized in time. Secondly, as for logical operations, since a hierarchical structure necessarily leads to longer logical operation timescales, leveraging the parallelizability of logical measurements and the capability of measuring long logical operators will be important for achieving higher logical processing throughput. Alternative ways to perform logical operations on an HLPsuch as transversal logical gates at level 1 assisted by level-1 flag qubits [57]–[60]are also worth investigation. Moreover, a careful study is needed to understand how HLPs and external cores can cooperate to solve quantum tasks with high efficiency. Finally, it is important to consider the hardware implementation of an HLP. For instance, one promising candidate is the local-CZ-based architecture [61]–[63] for neutral atoms, which allows in-place implementation of entangling gates in the level-0 SE without atom shuttling. It would be interesting to explore whether this architecture offers a significant speedup for our HLP compared to the zone-based architecture [20], [64].
NoteSee the public repository [65] for circuits and source codes used in our numerical experiments.
Related worksAfter completing this manuscript, we became aware of two recent related works [66], [67]. Ref. [66] studies a hierarchical logical memory architecture based on concatenating an algebraic code with a qLDPC code, using a bivariate bicycle code as the level-0 code and logical cat states for level-1 syndrome extraction. Ref. [67] introduces ‘dense-packing’, a variant of the surface code with densely packed twist defects, achieving \(2\times\) encoding rate of the rotated surface code. Ref. [67] further studies the concatenation of Iceberg codes with dense-packing in a similar manner to yoked surface codes [1]. In contrast, our work develops a transversal-gate-based hierarchical logical processor (HLP) architecture built on the rotated surface code, featuring short level-1 syndrome extraction time (measured in level-0 syndrome extraction rounds) and highly parallel logical measurements. We additionally perform full circuit-level simulations of several concrete HLP constructions. Overall, these works [66], [67] and ours are largely complementary: together they explore different hardware assumptions, level-0 code choices, and hierarchical structures toward the common goal of reducing the resource overhead of FTQC with moderate demands on hardware platforms.

We present a detailed description of the hierarchical logical processor (HLP) architecture in the supplementary material. In Sec. 1 , we describe basic modules for an HLP and its decoding procedure. In Sec. 2, we analyze the induced level-1 error model from level-0 errors. We prove that the correlation between level-1 \(X\) (or \(Z\)) errors can be effectively suppressed. In Sec. 3, we prove that our logical \(X\) (or \(Z\)) measurement protocol (with an LMS) achieves full level-1 distance. We then upper bound the probability of logical measurement errors for LMSs using the induced level-1 error model analyzed in Sec. 2. We describe the construction of two additional readout gadgets, the \(H\)-transformed readout gadget and the \(HS\)-transformed readout gadget. For LMSs based on \(H\)-transformed readout gadgets, we prove similar results to \(X\)-basis (or \(Z\)-basis) LMSs. We describe the extension of hybrid-unit CNOT gates to enable interfacing an HLP with external cores. In Sec. 4, we describe details on numerical simulations, including circuit-level simulations, soft-output simulations, and logical error rate extrapolation. See the public repository [65] for circuits and source codes used in our numerical experiments.

1 Hierarchical Logical Processor: Basic Modules↩︎

Our HLP essentially implements fault-tolerant logical operations (preserving logical information and measuring logical Pauli operators) on a concatenated codelogical information is encoded in a level-1 high-rate CSS code \(\mathcal{C}_1\) with a distance of \(d_1\), which is run on top of the level-0 distance-\(d_0\) RSC. In this section, we describe key components for our HLP and how to perform level-1 SE and logical Pauli \(X\) or \(Z\) measurements. We describe extensions to these modules, including performing general logical Pauli measurements and interfacing with logical information directly encoded in external RSC patches (external cores), in later sections.

1.1 Cores, shuttle buses, and hybrid-unit CNOT gates↩︎

An HLP consists of two working units: cores and shuttle buses, both of which are code patches whose logical qubits serve as level-1 qubits. Every level-1 data qubit of \(\mathcal{C}_1\) is the logical qubit of a distance-\(d_{0}\) RSC patch, referred to as a core. Every level-1 ancilla qubit for level-1 SE and logical Pauli measurements in our HLP is the logical qubit of an elongated RSC patch, referred to as a shuttle bus. We require each shuttle bus to have a width of \(d_0\) and a length of \(d_0d_1\). We note that our specific choice here is for a clean presentation of results, and that it is possible to use shuttle buses of different widths and lengths. A shuttle bus whose logical \(X\) (or \(Z\)) operator is supported on the long edge is called an \(X\) (or \(Z\)) bus. See Fig. 4 for an illustration of cores, \(X\) buses, and \(Z\) buses. We can perform (with a depth-1 layer of physical CNOT gates) transversal logical CNOT gates with an \(X\) (or \(Z\)) bus on the control side (or target side) and up to \(d_1\) cores on the target side (or control side). We refer to a depth-1 layer of physical CNOT gates implementing logical CNOT gates between (up to \(d_1\)) cores and a shuttle bus as a hybrid-unit CNOT gate. More specifically, a hybrid-unit CNOT gate between an \(X\) (or \(Z\)) bus and up to \(d_1\) cores is called a bus-core (or core-bus) CNOT gate.

1.2 Circuit structure and error model↩︎

Level-0 circuit structureFor conceptual simplicity and hardware friendliness, we implement level-0 SE rounds on cores and shuttle buses synchronously and require that there is at most a depth-1 layer of hybrid-unit CNOT gates between every two consecutive level-0 SE rounds. We refer to each level-0 SE round with its preceding depth-1 layer of hybrid-unit CNOT gates (if any) as a level-0 time step. We now define the (time-like) separation between two hybrid-unit CNOT gates.

We merge transversal initialization (or measurement) on a shuttle bus into the following (or preceding) level-0 SE round on the working unit. A shuttle bus is activated by the transversal initialization and deactivated by the transversal measurement. A deactivated shuttle bus will no longer be activated again. Instead, we reallocate all qubits of a deactivated shuttle bus to activate new shuttle buses later. We define the lifetime of a shuttle bus as the period between the level-0 time step at which the shuttle bus is initialized and the level-0 time step at which the shuttle bus is measured.

Level-1 circuit structureEvery level-0 circuit on cores and shuttle buses induces a corresponding level-1 circuit that represents operations on logical qubits of these working units. More specifically, level-0 SE rounds correspond to idling operations at level 1; transversal initialization and measurement on shuttle buses correspond to reset and measurement operations on their corresponding logical qubits at level 1; hybrid-unit CNOT gates correspond to level-1 CNOT gates. In every layer of a level-1 circuit, each level-1 qubit (corresponding to the logical qubit of a working unit) participates in one type of level-1 operation. Since each hybrid-unit CNOT gate can simultaneously couple a level-1 ancilla with up to \(d_1\) level-1 data qubits, we require that in every level-1 layer, (i) every level-1 data qubit participates in at most one CNOT gate with a level-1 ancilla and (ii) every level-1 ancilla qubit on an \(X\) (or \(Z\)) bus participates in at most \(d_1\) CNOT gates on the control side (or target side).

Perfect time boundariesThroughout this work, we consider HLPs with perfect initialization and measurement. More specifically, an HLP is initialized by (i) measuring all level-0 and level-1 stabilizers perfectly and (ii) measuring a collection of logical Pauli operators perfectly according to the logical initialization basis. Similarly, the final measurement on an HLP applies the same perfect measurement procedure used during perfect initialization.

Uniform depolarizing circuit noise modelThis model is a standard circuit-level noise model used for benchmarking fault-tolerant protocols. We perform all numerical simulations on level-0 circuits using this circuit noise model, with error locations listed as follows.

• Each single-qubit initialization in \(X\) (or \(Z\)) basis is followed by a single-qubit \(Z\) (or \(X\)) error with probability \(p\).

• Each single-qubit measurement in \(X\) (or \(Z\)) basis is preceded by a single-qubit \(Z\) or (\(X\)) error with probability \(p\).

• Each single-qubit gate (including idling) is followed by a single-qubit depolarizing channel with noise strength \(p\), consisting of three independent Pauli errors \(\{X,Y,Z\}\), each with probability \(p/3\).

• Each two-qubit gate is followed by a two-qubit depolarizing channel with noise strength \(p\), consisting of 15 independent Pauli errors \(\{I,X,Y,Z\}^{\otimes2}\backslash\{II\}\), each with probability \(p/15\).

• Each single-qubit measurement result is flipped with probability \(p\).

Phenomenological depolarizing noise modelIn this noise model, errors may only occur on level-0 data qubits at the beginning of each level-0 time step and on level-0 measurement results. We regard an \(X\)-basis (or \(Z\)-basis) measurement error as a \(Z\) (or \(X\)) error. The error locations are listed as follows.

• For each working unit \(\sigma\) at the beginning of every level-0 time step, if \(\sigma\) is transversally initialized in the \(X\) (or \(Z\)) basis, then every data qubit of \(\sigma\) experiences a Pauli \(Z\) (or \(X\)) error with probability \(p\) following the transversal initialization. Otherwise, every data qubit experiences a single-qubit depolarizing channel with noise strength \(p\).

• Every measurement result is flipped with probability \(p\).

1.3 Level-1 readout gadget↩︎

An \(X\)-basis (or \(Z\)-basis) readout gadget performs a projective measurement on a level-1 Pauli \(X\) (or \(Z\)) operator on level-1 data qubits with a level-1 ancilla implemented by an \(X\) bus (or \(Z\) bus). More specifically, for a level-1 Pauli \(X\) operator \(\mathsf{P}_{x}:=\mathsf{X}_1^{x_1}\otimes\cdots\otimes\mathsf{X}_{n_1}^{x_{n_1}}\) where \(x:=(x_1,\cdots,x_{n_1})\) is a vector in \(\mathbb{Z}_2^{n_1}\), the level-1 circuit of an \(X\)-basis readout gadget to measure \(\mathsf{P}_{x}\) proceeds as follows:

1. Initialize the level-1 ancilla in the \(X\) basis.

2. Perform a sequence of CNOT gates between the level-1 ancilla (control) and level-1 data qubits (target), such that for every level-1 data qubit \(i\) with \(x_i=1\), there is exactly one CNOT gate between this level-1 data qubit and the level-1 ancilla. Every level-1 layer of CNOT gates has at most \(d_1\) level-1 data qubits on the target side.

3. Measure the level-1 ancilla in the \(X\) basis.

Similarly, the level-1 circuit of a \(Z\)-basis readout gadget to measure a level-1 Pauli \(Z\) operator \(\mathsf{P}_z:=\mathsf{Z}_1^{z_1}\otimes\cdots\otimes\mathsf{Z}_{n_1}^{z_{n_1}}\) with \(z:=(z_1,\cdots,z_n)\in\mathbb{Z}_2^{n_1}\) proceeds as follows:

1. Initialize the level-1 ancilla in the \(Z\) basis.

2. Perform a sequence of CNOT gates between level-1 data qubits (control) and the level-1 ancilla qubit (target), such that for every level-1 data qubit \(i\) with \(z_i=1\), there is exactly one CNOT gate between this level-1 data qubit and the level-1 ancilla. Every level-1 layer of CNOT gates has at most \(d_1\) level-1 data qubits on the control side.

3. Measure the level-1 ancilla in the \(Z\) basis.

We now describe the level-0 implementation of an \(X\)-basis (or \(Z\)-basis) readout gadget. The level-1 ancilla of the readout gadget is the logical qubit of the shuttle bus associated with the gadget. Initialization and measurement on the level-1 ancilla in the \(X\) or \(Z\) basis are implemented by transversal initialization and measurement on the corresponding shuttle bus, respectively. Every level-1 layer of CNOT gates in the readout gadget is implemented by a hybrid-unit CNOT gate. We insert padding level-0 SE rounds on the shuttle bus so that (i) every two adjacent hybrid-unit CNOT gates in the readout gadget are separated by at least \(\alpha_{\mathsf{b}}d_{0}\) level-0 SE rounds and (ii) transversal reset (or measurement) of the shuttle bus is separated from the following (or preceding) hybrid-unit CNOT gate by at least \(\alpha_{\mathsf{b}}d_{0}\) rounds. Note that level-0 \(X\) (or \(Z\)) errors on \(X\) (or \(Z\)) buses may propagate to cores via hybrid-unit CNOT gates, thereby inducing correlated errors at level 1. The parameter \(\alpha_{\mathsf{b}}\) should therefore be chosen to suppress such error correlations. Moreover, the level-1 measurement result, referred to as the readout value, of a readout gadget may not be reliable, since a logical \(X\) (or \(Z\)) error on the \(Z\) (or \(X\)) bus of a \(Z\)-basis (or \(X\)-basis) readout gadget would flip the readout value, causing a readout error.

Readout gadgets (each with its own shuttle bus) can be juxtaposed, interleaved, or sequentially performed to implement an HLP. As mentioned in Sec. 1.2, hybrid-unit CNOT gates in readout gadgets should not overlap at any level-0 time step to guarantee that the level-0 implementation has at most a depth-1 layer of physical CNOT gates at the beginning of each level-0 time step. We define the separation between two readout gadgets as follows.

1.4 Basic Modules I: logical memory↩︎

The most fundamental functionality of an HLP is to protect quantum information by performing SE on the level-1 code \(\mathcal{C}_1\). We perform each level-1 SE round by measuring the same set of level-1 stabilizers, with each stabilizer measured using a readout gadget. Note that once a readout gadget is completed, the qubits used for its shuttle bus are now available again for a new readout gadget. Thus, we can trade off between the qubit overhead for readout gadgets and time overhead for a level-1 SE round by limiting the number of level-1 stabilizers measured in parallel. We require that every two \(X\)-basis (or \(Z\)-basis) readout gadgets for level-1 SE should be separated by at least \(\alpha_{\mathsf{c}}d_0\) level-0 time steps, where \(\alpha_{\mathsf{c}}\) is a positive parameter. As discussed in the main text, level-0 \(X\) (or \(Z\)) errors on cores may induce correlated \(X\) (or \(Z\)) errors on \(Z\) (or \(X\)) buses via hybrid-unit CNOT gates, thereby inducing correlated readout errors on \(Z\)-basis (or \(X\)-basis) readout gadgets. The parameter \(\alpha_{\mathsf{c}}\) is chosen to suppress correlations among readout errors.

We refer to the parameters \(\alpha_{\mathsf{b}}\) and \(\alpha_{\mathsf{c}}\) as compilation parameters. We later prove (under the phenomenological depolarizing noise model) that we can effectively suppress correlations among level-1 errors by setting \(\alpha_{\mathsf{c}}=1\) and \(\alpha_{\mathsf{b}}=d_1\). Larger compilation parameters imply sparser hybrid-unit CNOT gates and lower requirements on long-range connectivity, while also resulting in longer level-1 SE round time. Choosing these parametersbalancing level-1 round time, level-1 error correlation, and demand on long-range connectivityis subtle and requires extensive numerical study.

1.5 Basic Modules II: logical \(X\) or \(Z\) measurements↩︎

We use a sequence of \(X\)-basis (or \(Z\)-basis) readout gadgets, called a logical measurement sequence (LMS), to reliably measure a single logical \(X\) (or \(Z\)) operator. We refer to readout gadgets in an LMS as logical readout gadgets. More specifically, to measure an \(X\)-basis (or \(Z\)-basis) logical operator \(\mathsf{P}\), an LMS consists of \(d_1\) \(X\)-basis (or \(Z\)-basis) logical readout gadgets \(\mathsf{R}_1,\cdots,\mathsf{R}_{d_1}\), sequentially placed in \(d_1\) contiguous level-1 SE rounds from \(\mathsf{t}\) to \(\mathsf{t}+d_{1}-1\), such that each logical readout gadget \(\mathsf{R}_{j}\) (\(j\in\{1,\cdots,d_1\}\)) measures \(\mathsf{P}\) and is embedded in the level-1 SE round \(\mathsf{t}+j-1\). Moreover, we require that every \(X\)-basis logical readout gadget is separated from \(X\)-basis readout gadgets for level-1 SE and other logical readout gadgets in the same LMS by at least \(\alpha_{\mathsf{c}}d_{0}\) level-0 SE rounds. When measuring multiple (mutually commuting) logical operators in parallel, \(X\)-basis (or \(Z\)-basis) logical readout gadgets from different LMSs are allowed to be separated by as little as one level-0 time step. This enables parallel logical measurements at the cost of additional shuttle buses and increased use of long-range connectivity for hybrid-unit CNOT gates.

1.6 Detectors and decoding↩︎

There are two levels of detectors for an HLP: level-0 detectors directly generated from level-0 SE rounds in the level-0 circuit and level-1 detectors induced by the level-1 circuit. Note that since an HLP is implemented physically by the level-0 circuit, level-1 detectors are also compiled into sums over level-0 measurement results. In the following, we describe how to set up detectors and perform decoding for an HLP with basic modules described in the previous two subsections.

Level-0 detectorsThe construction of level-0 detectors is essentially the same as constructing detectors on circuits composed of SE and transversal CNOT gates on the RSC. Every level-0 detector is supported on measurement results in up to two adjacent level-0 time steps. Consider two adjacent level-0 time steps \(t-1\) and \(t\). If there are no hybrid-unit CNOT gates at time step \(t\), for each level-0 X or Z stabilizer \(\mathrm{S}\) measured in both time steps \(t-1\) and \(t\), there is a level-0 detector \(\mathrm{D}(\mathrm{S},t):=m_{\mathrm{S},t-1}\oplus m_{\mathrm{S},t}\), where \(\oplus\) is the XOR operator; \(m_{\mathrm{S},t-1}\) and \(m_{\mathrm{S},t}\) denote measurement results of \(\mathrm{S}\) at time steps \(t-1\) and \(t\), respectively; and \(t\) also denotes the time coordinate of the detector. On the other hand, suppose there is a layer of hybrid-unit CNOT gates \(\Lambda_t\) at time step \(t\). Through the gate \(\Lambda_{t}\), a stabilizer \(\mathrm{S}\) on a working unit propagates to \(\Lambda_t\mathrm{S}\Lambda_t^{\dagger}\), which we denote as \(\Lambda_t(\mathrm{S})\). Since \(\Lambda_t(\mathrm{S})\) is a product of stabilizer generators, we will also use it to denote the set of these stabilizer generators. Then, in this case, the level-0 detector corresponding to \(\mathrm{S}\) generated at time step \(t\) is \(\mathrm{D}(\mathrm{S},t):=m_{\mathrm{S},t-1}\oplus\left(\oplus_{\mathrm{S'}\in\Lambda_t(\mathrm{S})}m_{\mathrm{S}',t}\right)\).

Level-1 detectorsLevel-1 detectors are induced by readout gadgets for level-1 SE and level-1 logical measurements. For every two adjacent level-1 SE rounds \(\mathsf{t}\) and \(\mathsf{t}+1\), the two readout gadgets for each level-1 stabilizer \(\mathsf{S}\) induce a level-1 detector. Every two adjacent logical readout gadgets in an LMS induce a level-1 detector.

Level-0 decoding hypergraphLet \(\mathcal{E}\) be the set of all level-0 single-qubit \(X\) and \(Z\) error locations; let \(\mathcal{D}_{0}\) be the set of all level-0 detectors; let \(\mathcal{D}_1\) be the set of all level-1 detectors. Configurations of errors (subsets of \(\mathcal{E}\)), configurations of level-0 syndromes (subsets of \(\mathcal{D}_0\)), and configurations of level-1 syndromes (subsets of \(\mathcal{D}_1\)) are naturally identified with vectors in \(\mathbb{Z}_2^{|\mathcal{E}|}\), \(\mathbb{Z}_2^{|\mathcal{D}_{0}|}\), and \(\mathbb{Z}_2^{|\mathcal{D}_1|}\), respectively. Define syndrome maps \(\partial_{0}:\mathbb{Z}_2^{|\mathcal{E}|}\to\mathbb{Z}_2^{|\mathcal{D}_{0}|}\) and \(\partial_{1}:\mathbb{Z}_2^{|\mathcal{E}|}\to\mathbb{Z}_2^{|\mathcal{D}_{1}|}\), representing level-0 and level-1 syndromes of errors, respectively. There are three types of errors in \(\mathcal{E}\).

1. Canonical graphlike errors. A canonical graphlike error refers to an error that (i) has at most two endpoints and (ii) all its endpoints are on the same core or shuttle bus.

2. Decomposable hyperedge errors. A decomposable hyperedge error refers to an error that (i) can be decomposed into canonical graphlike errors and (ii) has endpoints over exactly two units, a core and a shuttle bus.

3. Primitive hyperedge errors. A primitive hyperedge error refers to an error that cannot be decomposed into canonical graphlike errors.

A primitive hyperedge error is always associated with a hybrid-unit CNOT gate. Consider a primitive hyperedge \(X\) error \(e\) in level-0 time step \(t\), then there is a hybrid-unit CNOT gate \(\Lambda_t\) at time step \(t\) such that the error \(e\) occurs on a working unit \(\sigma\) on the control side of \(\Lambda_t\). Moreover, this error triggers three \(Z\) detectors \(\mathrm{D}_{1}\), \(\mathrm{D}_2\), and \(\mathrm{D}_{3}\), such that the first two detectors are on the unit \(\sigma\) with time coordinates \(t\) and \(t+1\), respectively, and the third one is on a different working unit \(\sigma'\) on the target side of \(\Lambda_t\) with a time coordinate \(t\). We say the detector \(\mathrm{D}_{3}\) is on the pointy end of \(e\). Similar statements hold for primitive hyperedge \(Z\) errors.

Let \(\mathcal{E}_{0}\) be the collection of all canonical graphlike errors and primitive hyperedge errors in \(\mathcal{E}\). We construct the level-0 decoding hypergraph \(\mathcal{G}_0\) with the vertex set \(\mathcal{D}_{0}\) and the hyperedge set \(\mathcal{E}_{0}\). Every hyperedge \(e\in\mathcal{E}_{0}\) is connected exactly to all vertices in \(\partial_{0}e\). Note that our analysis of single-qubit \(X\) and \(Z\) errors above already encapsulates all two-qubit \(X\) and \(Z\) errors, since a two-qubit \(X\) (or \(Z\)) error following a CNOT gate is equivalent to a single-qubit \(X\) (or \(Z\)) error preceding the CNOT gate.

Level-0 decoding graphsLet \(\mathcal{D}_{\mathsf{B}_{\lozenge}}\) be the collection of all level-0 \(Z\) detectors on \(X\) buses and \(X\) detectors on \(Z\) buses; let \(\mathcal{D}_{\mathsf{C}}\) be the collection of all level-0 detectors on cores; let \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\) be the collection of all level-0 \(X\) detectors on \(X\) buses and \(Z\) detectors on \(Z\) buses. Similarly, for errors in \(\mathcal{E}_{0}\), let \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\) be the collection of all \(X\) errors on \(X\) buses and \(Z\) errors on \(Z\) buses; let \(\mathcal{E}_{\mathsf{C}}\) be the collection of all \(X\) and \(Z\) errors on cores; let \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\) be the collection of all \(Z\) errors on \(X\) buses and \(X\) errors on \(Z\) buses. For a level-0 syndrome configuration \(\eta\in\mathbb{Z}_2^{|\mathcal{D}_{0}|}\), denote its restriction to \(\mathcal{D}_{\mathsf{B}_{\lozenge}}\), \(\mathcal{D}_{\mathsf{C}}\), and \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\) as \(\eta|_{\mathsf{B}_{\lozenge}}\), \(\eta|_{\mathsf{C}}\), and \(\eta|_{\mathsf{B}_{\blacklozenge}}\), respectively. Similarly, for a level-0 error configuration \(\epsilon\in\mathbb{Z}_2^{|\mathcal{E}_{0}|}\), denote its restriction to \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\), \(\mathcal{E}_{\mathsf{C}}\), and \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\) as \(\epsilon|_{\mathsf{B}_{\lozenge}}\), \(\epsilon|_{\mathsf{C}}\), and \(\epsilon|_{\mathsf{B}_{\blacklozenge}}\), respectively.

From a level-0 decoding hypergraph \(\mathcal{G}_{0}\) for a level-0 circuit, we now construct three level-0 decoding graphs \(\mathcal{G}_{\mathsf{B}_{\lozenge}}\), \(\mathcal{G}_{\mathsf{C}}\), and \(\mathcal{G}_{\mathsf{B}_{\blacklozenge}}\) with vertex sets \(\mathcal{D}_{\mathsf{B}_\lozenge}\), \(\mathcal{D}_{\mathsf{C}}\), and \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\), respectively. Edges for the decoding graphs \(\mathcal{G}_{\mathsf{B}_{\lozenge}}\), \(\mathcal{G}_{\mathsf{C}}\), and \(\mathcal{G}_{\mathsf{B}_{\blacklozenge}}\) have one-to-one correspondence to level-0 errors in \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\), \(\mathcal{E}_{\mathsf{C}}\), and \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\), respectively, such that every error \(e\) in \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\) (or \(\mathcal{E}_{\mathsf{C}}\) or \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\)) corresponds to an edge in \(\mathcal{G}_{\mathsf{B}_{\lozenge}}\) (or \(\mathcal{G}_{\mathsf{C}}\) or \(\mathcal{G}_{\mathsf{B}_{\blacklozenge}}\)) with endpoints \((\partial_{0}e)|_{\mathsf{B}_\lozenge}\) (or \((\partial_0e)|_{\mathsf{C}}\) or \((\partial_{0}e)|_{\mathsf{B}_{\blacklozenge}}\)). By construction, every canonical graphlike error in \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\) (or \(\mathcal{E}_{\mathrm{C}}\) or \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\)) has a level-0 syndrome contained in \(\mathcal{D}_{\mathsf{B}_{\lozenge}}\) (or \(\mathcal{D}_{\mathsf{C}}\) or \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\)); every primitive hyperedge error in \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\) (or \(\mathcal{E}_{\mathrm{C}}\) or \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\)) triggers two detectors in \(\mathcal{D}_{\mathsf{B}_{\lozenge}}\) (or \(\mathcal{D}_{\mathsf{C}}\) or \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\)).

Consider a working unit \(\sigma\). If \(\sigma\) is a core, define the \(X\)-basis (or \(Z\)-basis) decoding subgraph on \(\sigma\) as the subgraph of \(\mathcal{G}_{\mathsf{C}}\) induced by the vertex set of all level-0 \(X\) (or \(Z\)) detectors on \(\sigma\). If \(\sigma\) is an \(X\) bus, define the \(X\)-basis (or \(Z\)-basis) decoding subgraph on \(\sigma\) as the subgraph of \(\mathcal{G}_{\mathsf{B}_{\blacklozenge}}\) (or \(\mathcal{G}_{\mathsf{B}_{\lozenge}}\)) induced by the vertex set of all level-0 \(X\) (or \(Z\)) detectors on \(\sigma\). We similarly make these definitions for \(Z\) buses. Define the \(X\)-basis (or \(Z\)-basis) segment on \(\sigma\) between level-0 time steps \(t_{0}\) and \(t_{1}\) (including both \(t_{0}\) and \(t_{1}\)) as the subgraph of the \(X\)-basis (or \(Z\)-basis) decoding subgraph on \(\sigma\) induced by the vertex set of all level-0 \(X\) (or \(Z\)) detectors with time coordinates between \(t_{0}\) and \(t_{1}\). For every \(t_{0}\leq t\leq t_{1}\), we say the level-0 time step \(t\) is contained in this segment. We refer to a segment on a core (or a shuttle bus) as a core (or bus) segment.

Level-0 decoding subroutineSince \(X\) (or \(Z\)) buses are always on the control (or target) side of hybrid-unit \(\mathrm{CNOT}\) gates, we can see that (i) errors in \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\) are the only errors in \(\mathcal{E}_{0}\) that trigger level-0 detectors in \(\mathcal{D}_{\mathsf{B}_\lozenge}\), (ii) primitive hyperedge errors in \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\) may only have a pointy end in \(\mathcal{D}_{\mathsf{C}}\), (iii) primitive hyperedge errors in \(\mathcal{E}_{\mathsf{C}}\) may only have a pointy end in \(\mathcal{D}_{\mathsf{B}_\blacklozenge}\), and (iv) errors in \(\mathcal{E}_{\mathsf{B}_\blacklozenge}\) should always be canonical graphlike errors. Based on these structural properties of the three level-0 decoding graphs, we develop our level-0 decoding subroutine, Algorithm 5, that takes a level-0 syndrome configuration \(\eta\in\mathbb{Z}_2^{|\mathcal{D}_{0}|}\) induced by some level-0 error configuration \(\epsilon\in\mathbb{Z}_2^{|\mathcal{E}_{0}|}\) and infers a level-0 error event \(\kappa\in\mathbb{Z}_2^{|\mathcal{E}_{0}|}\) with \(\partial_0\kappa=\partial_0\epsilon=\eta\). While the error configuration \(\epsilon+\kappa\) triggers no level-0 syndrome, it may still trigger level-1 detectors and logical observables. We refer to the configuration \(\epsilon+\kappa\) as the residual error configuration after level-0 decoding; we then need to perform level-1 decoding, which will be described later.

Note that we can combine Algorithm 5 with correlated matching [68] to enhance the decoding performance by taking correlations between \(X\) and \(Z\) errors into account. More specifically, given a level-0 syndrome configuration induced by physical errors, we can first run Algorithm 5, then change the weights of all decoding graphs based on the output following the approach in Ref. [68], and finally run Algorithm 5 again on reweighted decoding graphs. The output of the second run of Algorithm 5 is taken as the level-0 decoding result. We call this procedure above the correlated level-0 decoding. We use the original level-0 decoding routine in Algorithm 5 for theoretical analysis and the correlated level-0 decoding for numerical benchmarking.

Level-1 errorsConsider a collection \(\mathcal{M}\) of readout gadgets, such that the separation between every two \(X\)-basis (or \(Z\)-basis) readout gadgets in \(\mathcal{M}\) is lower bounded by \(\alpha_{\mathsf{c}} d_{0}\) level-0 time steps. We now define level-1 error locations and assign each a corresponding segment. For every core \(\sigma\), readout gadgets in \(\mathcal{M}\) assign a sequence of core-bus CNOT gates \(\Lambda_{t_1},\cdots,\Lambda_{t_{i}}\) (at level-0 time steps \(t_{1}<\cdots<t_{i}\)) and a sequence of bus-core CNOT gates \(\Lambda_{t_{1}'},\cdots,\Lambda_{t'_{j}}\) acting on \(\sigma\) (at level-0 time steps \(t_{1}'<\cdots<t_{j}'\)). Between every two adjacent level-1 CNOT gates with \(\sigma\) on the control side (corresponding to core-bus CNOT gates \(\Lambda_{t_{c}}\) and \(\Lambda_{t_{c+1}}\) with \(c\in\{1,\cdots,i-1\}\)), we assign a level-1 \(X\) error location on the core and define the \(Z\)-basis segment on \(\sigma\) between level-0 time steps \(t_{c}+1\) and \(t_{c+1}\) as the associated segment for the level-1 error location. We assign another two level-1 \(X\) error locations on \(\sigma\), one before the first level-1 CNOT gate corresponding to the core-bus CNOT gate \(\Lambda_{t_1}\) and the other after the last level-1 CNOT gate corresponding to the core-bus CNOT gate \(\Lambda_{t_{i}}\). We define \(Z\)-basis segments on \(\sigma\) before level-0 time step \(t_{1}\) and after level-0 time step \(t_{i}+1\) as the associated segments for the first and the last level-1 \(X\) error locations on \(\sigma\), respectively. See Fig. 6 for an illustration of all level-1 \(X\) error locations set above. Similarly, for the sequence of bus-core CNOT gates, we assign level-1 \(Z\) error locations on the core and define an associated segment for each level-1 \(Z\) error location. For every \(X\) bus \(\sigma'\) of an \(X\)-basis readout gadget in \(\mathcal{M}\), we assign a level-1 \(Z\) error location on \(\sigma'\), which does not propagate out of \(\sigma'\) and only triggers a readout error on the readout gadget. We define the \(X\)-basis segment on \(\sigma'\) spanning over the lifetime of \(\sigma'\) as the associated segment for this level-1 \(Z\) error location. We similarly assign a level-1 \(X\) error location for the \(Z\) bus in every \(Z\)-basis readout gadget in \(\mathcal{M}\) and define the associated bus segment for the level-1 \(X\) error location. These level-1 error locations defined above allow us to perform level-1 decoding. Every level-1 \(X\) (or \(Z\)) error on a level-1 \(X\) (or \(Z\)) error location is called a primitive level-1 error. Every segment associated with a level-1 error location is called a canonical segment.

Every primitive level-1 \(X\) (or \(Z\)) error with an associated canonical segment on a working unit \(\sigma\) between level-0 time steps \(t_1\) and \(t_2\) is equivalent to a logical \(X\) (or \(Z\)) error (as a level-0 error configuration) on \(\sigma\) at the beginning of a level-0 time step \(t\) with \(t_1\leq t\leq t_2\). Let \(\mathsf{E}\) be the collection of all primitive level-1 errors. A level-1 error configuration (as a subset of \(\mathsf{E}\)) is naturally identified with a vector in \(\mathbb{Z}_2^{|\mathsf{E}|}\). Let \(\overline{\partial}_{1}:\mathbb{Z}_2^{|\mathsf{E}|}\to \mathbb{Z}_2^{|\mathcal{D}_1|}\) be the level-1 syndrome map. We construct a level-1 decoding hypergraph \(\mathsf{G}\) with the vertex set \(\mathcal{D}_1\) and the hyperedge set \(\mathsf{E}\), such that each hyperedge \(\mathsf{e}\in\mathsf{E}\) is exactly connected to vertices in \(\overline{\partial}_{1}\mathsf{e}\).

Soft outputs and level-1 error probabilityFor every level-1 error location, we can extract a soft output on the associated canonical segment during the level-0 decoding process to estimate the probability of this level-1 error. This error probability is then converted to the weight of the corresponding hyperedge in the level-1 decoding hypergraph. In the following, we briefly review how to extract the soft output [39] from a segment during a level-0 decoding shot with a sparse-blossom decoder [69]. Consider a non-negatively weighted decoding graph \(\mathcal{G}(w)\) (\(\mathcal{G}\) for short), with \(w\) the assignment of edge weights that maps each edge to a non-negative number. At the end of each decoding shot with a sparse-blossom decoder, a region \(\mathcal{R}\) (combined graph fill region [69]) with an associated radius map \(r\) is constructed on \(\mathcal{G}\), where \(\mathcal{R}\) is a collection of vertices in \(\mathcal{G}\) and \(r\) assigns each vertex in \(\mathcal{G}\) a non-negative radius. Based on the region, we define the postdecoding weight for each edge \(e\in\mathcal{E}\) as \(\tilde{w}(e):=\max(0,w(e)-\sum_{v\in\partial e}r(v))\), where \(\partial e\) denotes the endpoints of \(e\) (Fig. 7). Define a new graph \(\tilde{\mathcal{G}}(\tilde{w})\) with the same vertex and edge structure as \(\mathcal{G}\), and postdecoding weights for all edges.

We are now ready to describe the extraction of the soft output from a segment during a level-0 decoding routine. Consider an \(X\)-basis core segment on the core \(\mathsf{c}\) containing time steps between \(t_1\) and \(t_2\) as shown in Fig. 8.

There are two types of boundary edges (weight-1 edges) in the core segment, each corresponding to one of two opposing \(Z\) boundaries. We attach a virtual boundary vertex \(v_{bd,0}\) or \(v_{bd,1}\) to boundary edges corresponding to either boundary. After decoding on \(\mathcal{G}_{\mathsf{C}}\), we obtain a reweighted graph \(\tilde{\mathcal{G}}_{\mathsf{C}}\) by applying the postdecoding reweight procedure described above. The soft output corresponding to the segment is defined as the minimum path length from \(v_{bd,0}\) to \(v_{bd,1}\) on \(\tilde{\mathcal{G}}_{\mathsf{C}}\), and can be efficiently computed by Dijkstra’s algorithm [39]. Soft outputs for other canonical segments are extracted similarly.

Full decoding procedure Consider an HLP with \(X\)-basis and \(Z\)-basis LMSs under perfect time boundaries. Each LMS generates a logical observable representing the measurement result of the corresponding logical Pauli operator. Moreover, logical measurements at perfect time boundaries may generate additional logical observables. Let \(\mathsf{L}\) be the collection of all logical observables. See Algorithm 9 for the full decoding procedure. Intuitively, we first perform a round of level-0 decoding. Then, at level 1, we decode logical observables supported on logical measurements at time boundaries independently from the other logical observables generated by LMSs. We then decode the logical observable induced by each LMS independently.

2 Induced Level-1 Error Model↩︎

In this section, we theoretically study how physical errors under the phenomenological depolarizing noise model, together with the level-0 decoding result, induce level-1 errors. We first set up the necessary notation for later discussion.

Let \(\mathcal{E}_{\mathrm{dep}}\) be the collection of all primitive level-0 errors in the phenomenological depolarizing noise model. We refer to an element of \(\mathbb{Z}_2^{|\mathcal{E}_{\mathrm{dep}}|}\), which specifies a subset of \(\mathcal{E}_{\mathrm{dep}}\), as a general level-0 error configuration to distinguish it from vectors in \(\mathbb{Z}_2^{|\mathcal{E}_{0}|}\), which are called level-0 error configurations. Since \(\mathcal{E}_{0}\), containing only \(X\) and \(Z\) errors, is a subset of \(\mathcal{E}_{\mathrm{dep}}\), there is a natural injection from \(\mathbb{Z}_{2}^{|\mathcal{E}_{0}|}\) to \(\mathbb{Z}_2^{|\mathcal{E}_{\mathrm{dep}}|}\). Therefore, every level-0 error configuration is also a general level-0 error configuration. We use the same notation \(\partial_{0}\) and \(\partial_{1}\) for the syndrome maps extended from level-0 error configurations to general level-0 error configurations. Define a linear map \(\mathbb{P}_{\mathrm{X}}:\mathbb{Z}_2^{|\mathcal{E}_{\mathrm{dep}}|}\to\mathbb{Z}_2^{|\mathcal{E}_{0}|}\) that maps every primitive level-0 error in \(\mathcal{E}_{\mathrm{dep}}\) to its \(X\)-basis component in \(\mathcal{E}_{0}\). We similarly define \(\mathbb{P}_{\mathrm{Z}}:\mathbb{Z}_2^{|\mathcal{E}_{\mathrm{dep}}|}\to\mathbb{Z}_2^{|\mathcal{E}_{0}|}\). For a general level-0 error configuration \(g\), we define its \(X\)-basis (or \(Z\)-basis) component as \(g_{X}:=\mathbb{P}_{\mathrm{X}}(g)\) (or \(g_Z:=\mathbb{P}_{\mathrm{Z}}(g)\)).

Consider a configuration \(\epsilon\in\mathbb{Z}_2^{|\mathcal{E}_{\mathrm{dep}}|}\) of level-0 physical errors triggering level-0 detectors \(\eta=\partial_{0}\epsilon\). We use Algorithm 5 to obtain an inferred error configuration \(\kappa\in\mathbb{Z}_2^{|\mathcal{E}_{0}|}\) with \(\partial_{0}\kappa=\eta\). Let \(f:=\epsilon+\kappa\), which we call the general residual error configuration. Let \(\mathcal{M}\) be the collection of readout gadgets whose measurement results are of interest. We construct level-1 error locations for \(\mathcal{M}\) and let \(\mathsf{E}\) be the collection of primitive level-1 errors. Let \(\mathcal{D}_{\mathsf{B}_{\blacktriangledown}}\subset\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\) be the subset of detectors in \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\) on buses in \(\mathcal{M}\); let \(\mathcal{E}_{\mathsf{B}_{\blacktriangledown}}\) be the subset of errors in \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\) on buses in \(\mathcal{M}\). Let \(\partial_{\blacktriangledown}\) be the restricted level-0 syndrome map, which restricts level-0 syndromes to \(\mathcal{D}_{\mathsf{B}_{\lozenge}}\cup \mathcal{D}_{\mathsf{C}}\cup \mathcal{D}_{\mathsf{B}_{\blacktriangledown}}\). We note that level-0 errors in \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\backslash\mathcal{E}_{\mathsf{B}_{\blacktriangledown}}\) do not affect readout gadgets in \(\mathcal{M}\). We say two level-0 error configurations \(g_{1}\) and \(g_{2}\) are \(\mathcal{M}\)-equivalentdenoted as \(g_{1}\simeq_{\mathcal{M}}g_{2}\)if they differ by at most a space-time stabilizer (described later) and an error configuration in \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\backslash\mathcal{E}_{\mathsf{B}_{\blacktriangledown}}\).

In Sec. 2.1, we prove that \(f\) induces a level-1 error configuration in \(\mathbb{Z}_2^{|\mathsf{E}|}\). This observation guarantees the existence of a solution for our level-1 decoding procedurethe residual error after the level-0 decoding procedure indeed corresponds to a level-1 error configuration. Without loss of generality, we assume \(f\in\mathbb{Z}_2^{|\mathcal{E}_{0}|}\) by decomposing every \(Y\) error in \(\epsilon\) into its \(X\)- and \(Z\)-basis components. We will show that \(f|_{\mathsf{B}_{\lozenge}}\), the residual error restricted to \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\), is equivalent to a level-0 error configuration \(f^{\scriptscriptstyle\square}\) on cores. We say \(f^{\scriptscriptstyle\square}\) is the propagated error from \(f|_{\mathsf{B}_{\lozenge}}\). Then, the combination of the propagated error \(f^{\scriptscriptstyle\square}\) and \(f|_{\mathsf{C}}\) is shown to be \(\mathcal{M}\)-equivalent to the combination of a level-1 error configuration \(\mathsf{f}_{\mathsf{C}}\) on cores and a level-0 error configuration \(f^{\scriptscriptstyle\blacksquare}\) on shuttle buses in \(\mathcal{M}\). Similarly, we say \(f^{\scriptscriptstyle\blacksquare}\) is the propagated errors from \(f^{\scriptscriptstyle\square}+f|_{\mathsf{C}}\), restricted to shuttle buses in \(\mathcal{M}\). We will show that \(f^{\scriptscriptstyle\blacksquare}+f|_{\mathsf{B}_{\blacktriangledown}}\) induces a level-1 error configuration \(\mathsf{f}_{\mathsf{B}}\) on shuttle buses in \(\mathcal{M}\). Finally, we see that \(f\) induces the level-1 error configuration \(\mathsf{f}_{\mathsf{C}}+\mathsf{f}_{\mathsf{B}}\) (or equivalently, \(f\simeq_{\mathcal{M}}\mathsf{f}_{\mathsf{C}}+\mathsf{f}_{\mathsf{B}}\)).

In Sec. 2.2, we show the induced level-1 \(X\) (or \(Z\)) errors almost satisfy a local stochastic noise model.

2.1 Error propagation through hybrid-unit CNOT gates↩︎

We start with a general study of the error propagation phenomena and then analyze \(f\) in detail.

Space-time stabilizers and CNOT membranesA level-0 error configuration that triggers no (level-0 or level-1) detector or logical observable is called a space-time stabilizer [36], [44], [70]. We say two level-0 error configurations \(g_1\) and \(g_2\) are equivalent if they differ by a space-time stabilizer (this is stronger than \(\mathcal{M}\)-equivalence described above). We denote this equivalence relation as \(g_1\simeq g_2\). Thus, we can deform a level-0 error configuration into another equivalent configuration by multiplying the original configuration by space-time stabilizers. For a data qubit \(i\) on a working unit \(\sigma\), denote the collection of \(X\) (or \(Z\)) stabilizer generators of the working unit supported on qubit \(i\) as \(\delta_{X,i}\) (or \(\delta_{Z,i}\)). At a level-0 time step \(t\), let \(\Lambda_{t}\) denote the depth-1 layer of hybrid CNOT gates; let \(e_{A,i,t}\) denote the \(A\)-basis (\(A\in\{X,Z\}\)) data qubit error on qubit \(i\); let \(e_{\mathrm{S},t}\) denote the measurement error on stabilizer \(\mathrm{S}\). If qubit \(i\) is not acted on by \(\Lambda_{t}\), then \(X\) errors \(e_{X,i,t}\), \(e_{X,i,t+1}\) on this qubit at the level-0 time steps \(t\) and \(t+1\), together with stabilizer measurement errors \(\{e_{\mathrm{S},t}|\mathrm{S}\in\delta_{Z,i}\}\) at level-0 time step \(t\), form a spacetime stabilizer. Similarly, \(e_{Z,i,t}+e_{Z,i,t+1}+\sum_{\mathrm{S}\in \delta_{X,i}}e_{\mathrm{S},t}\) is also a spacetime stabilizer. Now consider the case where qubit \(i\) is acted on by \(\Lambda_{t}\). Denote the qubit that participated in the same physical CNOT gate as \(i\) in \(\Lambda_{t}\) as \(j\). If qubit \(i\) is on the target side of \(\Lambda_t\), then \(e_{Z,i,t}+e_{Z,i,t+1}+e_{Z,j,t}+\sum_{\mathrm{S}\in\delta_{X,i}}e_{\mathrm{S},t}\) is a spacetime stabilizer. Notice that the level-0 error configuration \(e_{Z,i,t}+e_{Z,i,t+1}+\sum_{\mathrm{S}\in\delta_{X,i}}e_{\mathrm{S},t}\) on the working unit \(\sigma\) is now equivalent to the qubit error \(e_{Z,j,t}\) on a different working unit. This gives rise to the error propagation phenomenon that we mentioned at the beginning of Sec. 2. We define a CNOT membrane associated with \(\Lambda_{t}\) for the \(X\)-basis decoding subgraph on the working unit \(\sigma\) as a plane with a time coordinate \(t+\frac{1}{2}\) (only in the coordinate system of the subgraph). We say every \(X\) stabilizer measurement error on \(\sigma\) at level-0 time step \(t\) is on the CNOT membrane. Moreover, we say a level-0 error configuration intersects with this CNOT membrane if the configuration contains at least one primitive level-0 error on the CNOT membrane. See Fig. 10 for an illustration of space-time stabilizers and a CNOT membrane.

Similarly, if qubit \(i\) is on the control side, then \(e_{X,i,t}+e_{X,i,t+1}+e_{X,j,t}+\sum_{\mathrm{S}\in\delta_{Z,i}}e_{\mathrm{S},t}\) is a spacetime stabilizer. In this case, we define a CNOT membrane associated with \(\Lambda_t\) on \(\sigma\) as a plane with a time coordinate \(t+\frac{1}{2}\) in the coordinate system of the \(Z\)-basis decoding subgraph for \(\sigma\).

Walks, paths, and cyclesBorrowing from standard terminologies of walks, paths, and cycles on a graph in graph theory [71], we define these terms as sequences of primitive level-0 errors on a decoding subgraph in the following. Consider an \(X\)- or \(Z\)-basis decoding subgraph for a working unit \(\sigma\). We introduce an additional virtual vertex \(v_{\varnothing}\) (representing the lack of a vertex), which is considered an endpoint for every boundary edge in the decoding subgraph. A walk \(\omega\) on the decoding subgraph is a sequence of primitive level-0 errors \(e_1,\cdots,e_{r}\) (each corresponds to an edge in the decoding subgraph), such that there is a sequence of vertices \(v_{0},\cdots,v_{r}\) on the decoding graph satisfying the following conditions: (i) only vertices \(v_{0}\) and \(v_{r}\) are allowed to be \(v_{\varnothing}\) (in other words, only \(e_{1}\) and \(e_{r}\) are allowed to be boundary edges), and (ii) for every \(i\in\{1,\cdots,r\}\), both \(v_{i-1}\) and \(v_{i}\) are endpoints of \(e_{i}\). The vertex sequence \(v_{0},\cdots,v_{r}\) is referred to as the vertex trail of \(\omega\). A subwalk of \(\omega\) is a subsequence of \(\omega\). Each walk \(\omega\) is associated with a level-0 error configuration, \([\omega]\), as the sum of all primitive level-0 errors in \(\omega\) as vectors over \(\mathbb{Z}_2\). This level-0 error configuration \([\omega]\) is called the error value of \(\omega\). If \(\omega\) contains no repeated primitive level-0 errors, then we can safely identify \(\omega\) with \([\omega]\). We let \(|\omega|\) denote the length of the sequence \(\omega\) and \(|[\omega]|\) denote the weight of \([\omega]\). Similarly, consider a collection of walks \(\overline{\omega}\), we define its error value \([\overline{\omega}]\) as the sum of all primitive level-0 errors in \(\overline{\omega}\) as vectors over \(\mathbb{Z}_2\). We also identify \(\overline{\omega}\) with \([\overline{\omega}]\) if \(\overline{\omega}\) contains no repeated level-0 primitive errors; we let \(|\overline{\omega}|\) denote the sum of lengths of all walks in \(\overline{\omega}\) and \(|[\overline{\omega}]|\) denote the weight of \([\overline{\omega}]\). We introduce two subscripts \(||\) and \(\perp\), representing the qubit-error component and the stabilizer-measurement-error component, respectively. In this way, \(|\overline{\omega}_{||}|\) and \(|\overline{\omega}_{\perp}|\) denote the number of occurrences of qubit errors and stabilizer measurement errors in \(\overline{\omega}\) (rather than in its error value \([\overline{\omega}]\)), respectively. Similarly, this definition also applies to individual walks and error configurations. We say a walk \(\omega\) is closed if the starting vertex coincides with the ending vertex in the vertex trail of \(\omega\). A simple walk is a walk with no repeated primitive level-0 errors. A walk \(\omega\) with its vertex trail \(v_{0},\cdots,v_{r}\) is a path if all these vertices are disjoint; the walk \(\omega\) is a cycle if the only repeated vertices in the vertex trail are \(v_{0}\) and \(v_{r}\). A closed walk can be decomposed as a collection of cycles; a walk that is not closed can be decomposed as a path and a collection of cycles. We note that every walk that we analyze in the following has no repeated primitive level-0 errors on any CNOT membrane.

Classification of closed walks on decoding graphsWe classify closed walks in an \(X\)-basis or \(Z\)-basis decoding subgraph on a working unit into the following categories.

1. Lightning walk. A lightning walk is a closed walk terminating at two opposite spatial boundaries. A canonical lightning walk is a lightning walk that does not intersect with any CNOT membrane.

2. Sprout walk. A sprout walk is a closed walk terminating at a time boundary. A benign sprout walk is a sprout walk that does not intersect with any CNOT membrane. A benign sprout walk does not propagate errors.

3. Cross-membrane walk. A cross-membrane walk is a closed walk that does not belong to the above two categories and intersects with at least one CNOT membrane.

4. Benign walk. A benign walk is a closed walk that does not belong to the above three categories. The error value of a benign walk is a level-0 space-time stabilizer.

We establish the following two lemmas. The first allows us to equivalently deform a lightning walk into a canonical lightning walk and a collection of benign and cross-membrane walks. The second shows that the error value of a sprout walk is equivalent to the combination of benign sprout cycles and cross-membrane cycles.

Error propagationIn the following, we show (i) how canonical \(X\)-basis (or \(Z\)-basis) lightning cycles on an \(X\) (or \(Z\)) bus propagate errors to cores through CNOT membranes, and (ii) how cross-membrane walks propagate errors through CNOT membranes. The latter is a recurrently used technique in Sec. 2.2.

We now return to the analysis of the level-0 residual error configuration \(f\in\mathbb{Z}_2^{|\mathcal{E}_{0}|}\) introduced at the beginning of this section.

2.2 Error Reduction Theorem↩︎

Throughout this subsection, we fix the compilation parameter \(\alpha_{\mathsf{b}}=d_{1}\) and ensure that every pair of \(X\)-basis or \(Z\)-basis readout gadgets in \(\mathcal{M}\) is separated by at least \(d_{0}\) level-0 time steps. In this case, we will show that the probability distribution of induced level-1 \(X\) (or \(Z\)) errors satisfies a local stochastic noise model except for a rare event whose probability is exponentially suppressed in \(d_{0}d_1\).

Without loss of generality, we consider level-1 \(X\) errors. For now, we assume that \(f\) consists only of level-0 \(X\) errors. We now perform a more fine-grained analysis on \(f\). According to the proof of Lemma 5, we know that there are two types of errors on cores: one is the propagated errors (each is a simple walk according to Lemma 4) from \(X\)-basis closed walks on \(X\) buses; the other is the native errors in \(f|_{\mathsf{C}}\). Similarly, there are two types of \(X\)-basis errors on \(Z\) buses: one propagated from cores and the other in \(f|_{\mathsf{B}_{\blacktriangledown}}\). We often need to consider propagated errors and native errors in \(f\) as distinct objects to track their respective weights. In this section, we regard \(f\) as a set of length-1 walks, referred to as native walks, each of which corresponds to a unique primitive level-0 error in \(f\). Then, every level-0 error configuration contained in \(f\) is regarded as a subset of \(f\). Propagated simple walks are treated as distinct objects and are not identified with native walks, even when they have overlapping supports.

We know that \(f|_{\mathsf{B}_{\lozenge}}\) is a collection of error cycles \(\{\tilde{\ell}_{1},\cdots,\tilde{\ell}_{r}\}\) on \(X\) buses. We restrict to the case where each cycle in \(f|_{\mathsf{B}_{\lozenge}}\) has a weight smaller than \(d_{0}d_{1}\). (The probability for a cycle of weight at least \(d_0d_1\) is so heavily suppressed that we can regard such an event as failure without analyzing it.) In this case, every cycle in \(f|_{\mathsf{B}_{\lozenge}}\) is either a benign sprout cycle, a benign cycle, or a cross-membrane cycle that only intersects with a single CNOT membrane. For each \(\tilde{\ell}_{i}\) (\(i\in\{1,\cdots,r\}\)), let \(\tilde{\ell}_{i}^{\circ}\) be a set of propagated simple walks, representing the propagated errors from \(\tilde{\ell}_i\). If \(\tilde{\ell}_i\) is a benign cycle or a benign sprout cycle, then \(\tilde{\ell}_i^{\circ}\) is an empty set. Otherwise, we obtain \(\tilde{\ell}_{i}^{\circ}\) as a set of propagated simple walks on cores, following Lemma 4. We say \(\tilde{\ell}_i\) is the source for every propagated simple walk in \(\tilde{\ell}_{i}^{\circ}\). Define \(f^{\circ}:=\bigcup \tilde{\ell}_i^{\circ}\), the collection of propagated simple walks on cores from \(\{\tilde{\ell}_1,\cdots,\tilde{\ell}_r\}\). We note that \(f^{\circ}\) may contain repeated level-0 primitive errors; thus, we need to differentiate the set from its error value \([f^{\circ}]\). Moreover, as \(\tilde{\ell}_i\simeq \tilde{\ell}_i^{\circ}\), we know that the error configuration \([f^{\circ}]\) is equivalent to \(f|_{\mathsf{B}_{\lozenge}}\). The propagated simple walks in \(f^{\circ}\), together with the native walks in \(f|_{\mathsf{C}}\), can be partitioned into a set of closed walks \(\{\ell_{1},\cdots,\ell_{o}\}\) on cores, such that (i) each closed walk \(\ell_{j}\) is composed of propagated simple walks in \(f^{\circ}\) and native walks in \(f|_{\mathsf{C}}\) and (ii) every simple walk in \(f^{\circ}\), as well as every native walk in \(f|_{\mathsf{C}}\), is contained in exactly one closed walk in \(\{\ell_{1},\cdots,\ell_{o}\}\). We also view each closed walk \(\ell_{j}\) as a set of the constituent propagated simple walks in \(f^{\circ}\) and native walks in \(f|_{\mathsf{C}}\). In this way, the disjoint union of two sets of walks \(f^{\circ}\cup f|_{\mathsf{C}}\) is also the disjoint union of \(\ell_{1},\cdots,\ell_{o}\).

For each \(\ell_j\), we will define its propagation \(\ell_j^{\bullet}\) as a set of simple walks on \(Z\) buses in \(\mathcal{M}\); and we also say \(\ell_j\) is the source for every simple walk in \(\ell_j^{\bullet}\). If \(\ell_j\) is a benign walk, then \(\ell_j^{\bullet}\) is an empty set. If \(\ell_j\) is a cross-membrane walk, define \(\ell_j^{\bullet}\) as the set of simple walks propagated from \(\ell_j\) according to Lemma 4. If \(\ell_i\) is a lightning walk, according to Lemma 1, we can find the canonical retraction \(g_j\) of \(\ell_j\), such that we can arrange \(\ell\) and paths in \(g_{i}\) into a collection of cross-membrane walks and benign walks. Define \(\ell_j^{\bullet}\) as the set of all simple walks propagated from these cross-membrane walks. Define \(f^{\bullet}:=\bigcup \ell_j^{\bullet}\) as the set of all simple walks on buses in \(\mathcal{M}\) propagated from \(\{\ell_1,\cdots,\ell_o\}\). Similarly, the set of walks \(f^{\bullet}\cup f|_{\mathsf{B}_{\blacktriangledown}}\) can be decomposed as a disjoint union of closed walks on \(Z\) buses. We refer to each such closed walk as a closed walk in \(f^{\bullet}\cup f|_{\mathsf{B}_{\blacktriangledown}}\). We say a closed walk in \(f^{\bullet}\cup f|_{\mathsf{B}_{\blacktriangledown}}\) is native if the closed walk only consists of native walks in \(f|_{\mathsf{B}_{\blacktriangledown}}\). We say two closed walks \(\ell_{a}\) and \(\ell_{b}\) on cores are linked if a simple walk in \(\ell_a^{\bullet}\) and a simple walk in \(\ell_{b}^{\bullet}\) belong to the same closed walk in \(f^{\bullet}\cup f|_{\mathsf{B}_{\blacktriangledown}}\) on a \(Z\) bus. We can then construct a graph \(\mathcal{W}_{\mathsf{C}}\) with closed walks in \(\{\ell_{1},\cdots,\ell_o\}\) as vertices, such that two vertices are connected by an edge if and only if the corresponding closed walks are linked.

In this way, we can see that \(f^{\circ}\cup( f|_{\mathsf{C}}\cup f|_{\mathsf{B}_{\blacktriangledown}})\) is a disjoint union of downstream webs and native closed walks on \(Z\) buses.

We now set bounds on native downstream webs and then set bounds on \(f\). We start with two definitions. First, we define a level-0 adjacency graph \(\mathcal{A}\) [7], whose vertices are identified with level-0 error locations, such that every two vertices are connected by an edge if and only if their corresponding primitive level-0 errors overlap in their level-0 syndromes. This construction [7] is a standard technique in fault-tolerance proofs to help with combinatorial analysis of errors. Secondly, we define sets of primitive level-0 \(X\) errors in \(\mathcal{E}_{0}\) that may contribute to primitive level-1 \(X\) errors on cores and \(Z\) buses, respectively.

Building on Lemma 6, we can now bound \(f\).

We previously considered only level-0 \(X\) error configurations in this subsection. Now, we allow \(f\) to be a general level-0 residual error configuration with \(f=\epsilon+\kappa\), where \(\epsilon\in\mathbb{Z}_2^{|\mathcal{E}_{\mathrm{dep}}|}\) is the physical error term and \(\kappa\in\mathbb{Z}_2^{|\mathcal{E}_{0}|}\) is the inferred error configuration. Let \(f_{\epsilon}:=f\cap \epsilon\) and \(f_{\kappa}:=f\cap\kappa\), representing physical errors and inferred errors in \(f\), respectively. Consider the \(X\)-basis projection \(f_{X}=\epsilon_{X}+\kappa_{X}\). In previous arguments, \(f_{X,\epsilon}:=f_{X}\cap\epsilon_{X}\) and \(f_{X,\kappa}:=f_{X}\cap\kappa_{X}\) represent physical errors and inferred errors in \(f_{X}\), respectively. We define similar notations for \(f_Z\). To relate subconfigurations in \(f_X\cup f_{Z}\) to subconfigurations in \(f\), we construct a section map \(\mathbb{S}_{f}\) that maps every subset (subconfiguration) in \(f_{X}\cup f_{Z}\) to a subset (subconfiguration) in \(f\) with the following four properties.

1. For each subconfiguration \(g\subset f_{X}\cup f_{Z}\), \(\mathbb{S}_{f}(g)=\bigcup_{e\in g} \mathbb{S}_{f}(e)\) with each \(e\) a primitive level-0 error in \(g\).

2. For each primitive error \(e_{X}\in f_{X}\), \(\mathbb{P}_{X}\circ \mathbb{S}_f(e_X)=e_X\). Similarly, for each primitive error \(e_{Z}\in f_{Z}\), \(\mathbb{P}_{Z}\circ \mathbb{S}_f(e_Z)=e_Z\).

3. For every \(g_X\subset f_{X,\epsilon}\), \(\mathbb{S}_{f}(g_X)\subset f_{\epsilon}\). For every \(g_X\subset f_{X,\kappa}\), \(\mathbb{S}_f(g_X)\subset f_{\kappa}\).

4. For every \(g_{Z}\subset f_{Z,\epsilon}\), \(\mathbb{S}_{f}(g_Z)\subset f_{\epsilon}\). For every \(g_Z\subset f_{Z,\kappa}\), \(\mathbb{S}_f(g_Z)\subset f_{\kappa}\).

By construction, we know that given a subconfiguration \(g\subset f_{X}\cup f_{Z}\), \(|\mathbb{S}_f(g)\cap \epsilon|\geq \max(|g_X\cap \epsilon_X|,|g_{Z}\cap\epsilon_{Z}|)\). Additionally, if \(g\) forms a connected cluster on the level-0 adjacency graph, then \(\mathbb{S}_{f}(g)\) also forms a connected cluster. Building on Lemma 7, we can bound a general level-0 residual error configuration.

We follow previous fault-tolerance proofs [7], [72], [73] (in particular, the ‘bad set’ formalism in Ref. [73]) to provide a sufficient condition for upper bounding level-1 error probabilities.

We will need the following lemma from Ref. [72] (widely used in fault-tolerance proofs to count the number of errors) to upper bound the number of elements of a certain weight in a set of error configurations.

We note that for our level-0 adjacency graph \(\mathcal{A}\), the degree of any vertex is upper bounded by \(48\), since each primitive level-0 error triggers up to \(4\) level-0 detectors, and each level-0 detector can be triggered by up to \(12\) distinct level-0 error locations.

3 Logical Pauli measurements↩︎

In this section, we analyze the performance of the LMSs constructed for measuring logical \(X\) and \(Z\) operators on an HLP. We then describe how to measure general logical Pauli operators with \(H\)-transformed and \(HS\)-transformed readout gadgets. We extend our analysis on the induced level-1 error model as well as LMSs to incorporate \(H\)-transformed gadgets. Finally, we extend hybrid-unit CNOT gates to enable transversal CNOT gates between shuttle buses and external cores. We tentatively propose a hybrid architecture where an HLP or possibly multiple HLPs work closely with external cores to run logical computation.

3.1 Performance analysis of LMSs for measuring logical \(X\) and \(Z\) operators↩︎

We first consider a single LMS consisting of \(d_{1}\) \(X\)-basis (or \(Z\)-basis) readout gadgets. Let \(\mathcal{M}\) be the collection of all logical readout gadgets in the LMS and all readout gadgets for level-1 SE. We construct a level-1 error model for \(\mathcal{M}\). We can lower bound the number of primitive level-1 errors required to trigger a logical measurement error in this LMS.

Now, we show that the probability of any LMS being faulty remains exponentially suppressed even when LMSs are densely packed. This theoretical guarantee enables parallel logical \(X\) or \(Z\) measurements. We first introduce definitions and notations to describe the level-1 structure of an HLP. Let \(n_1\) and \(s_{1}\) be the number of level-1 data qubits and the number of level-1 stabilizers measured in each level-1 SE round. Let \(\mathcal{M}_{\mathsf{SE}}\) denote the set of readout gadgets for level-1 SE. Define the degree of a level-1 data qubit as the number of level-1 stabilizers supported on this qubit that are measured in a level-1 SE round. Let \(\delta_1\) be the maximum degree of a level-1 data qubit in our HLP; let \(\varpi_1\) be the maximum weight of measured level-1 stabilizers.

We note that for a low enough error rate \(p\), Theorem 3 upper bounds the probability of logical measurement errors by \(\sim p^{d_{0}d_{1}/4}\), while for an HLP achieving full distance, the scaling of logical measurement errors should ideally be \(\sim p^{d_0d_1/2}\). We attribute the discrepancy here to our proof technique, which separately analyzes level-0 and level-1 errors. More specifically, by analyzing level-0 errors, Theorem 2 proves that the effective level-1 error probability \(p_1\) scales as \(\sim p^{d_{0}/2}\), indicating that full level-0 distance is achieved. Then, with this level-1 error rate, the probability of logical measurement errors at best scales as \(\sim p_1^{d_{1}/2}\sim p^{d_{0}d_{1}/4}\) even when full level-1 distance is achieved. In contrast, our decoding procedure (Algorithm 9) extracts soft information from level-0 decoding and applies this information to level-1 decoding, thereby effectively coupling the level-0 and level-1 decoding procedures. As a result, our circuit-level simulations in Fig. 2 (b) and Fig. 3 (c) indicate HLPs therein are operating close to their full distance.

3.2 Extension module I: measuring general level-1 logical Pauli operators↩︎

Consider a logical operator \(\mathsf{P}_{xz}:=i^{x\cdot z}\mathsf{X}_{1}^{x_1}\mathsf{Z}_1^{z_1}\otimes \cdots\otimes \mathsf{X}_{n_1}^{x_{n_1}}\mathsf{Z}_{n_1}^{z_{n_1}}\), where \(x=(x_1,\cdots,x_{n_1})\) and \(z=(z_{1},\cdots,z_{n_1})\) are vectors in \(\mathbb{Z}_2^{n_1}\). When \(x\cdot z\) is even, we construct the \(H\)-transformed readout gadget which proceeds as follows (see also Fig. 3 (d)):

1. Initialize the level-1 ancilla in the \(Z\) basis.

2. Perform a sequence of CNOT gates between level-1 data qubits (controls) and the level-1 ancilla qubit (target), such that for every level-1 data qubit \(i\) with \(z_i=1\), exactly one CNOT gate is applied between that qubit and the ancilla. Every level-1 layer has at most \(d_1\) control qubits.

3. Perform a level-1 \(H\) gate on the ancilla.

4. Perform a sequence of CNOT gates between the level-1 ancilla (control) and level-1 data qubits (targets), such that for every level-1 data qubit \(i\) with \(x_i=1\), exactly one CNOT gate is applied between that qubit and the ancilla. Every level-1 layer has at most \(d_1\) target qubits.

5. Measure the level-1 ancilla in the \(X\) basis.

We now describe the level-0 implementation of an \(H\)-transformed readout gadget. The level-1 ancilla of the gadget is implemented by a shuttle bus, referred to as an \(H\) bus. In the first step, the \(H\) bus is transversally initialized in the \(Z\) basis as a \(Z\) bus. Then, the sequence of level-1 CNOT gates between level-1 data qubits (controls) and the level-1 ancilla (target) is implemented by core-bus CNOT gates between the corresponding cores and the \(H\) bus. In the third step, we apply a layer of transversal \(H\) gates on all data qubits of the \(H\) bus, thereby implementing a logical \(H\) gate on the level-1 ancilla and transforming the bus into an \(X\) bus. We group this layer of transversal \(H\) gates with the following level-0 SE round as a level-0 time step. Similarly, level-1 CNOT gates in the fourth step are implemented by bus-core CNOT gates between the \(H\) bus (control) and cores (targets). Finally, the \(H\) bus is transversally measured in the \(X\) basis. Similar to \(X\)-basis and \(Z\)-basis readout gadgets, we insert padding level-0 SE rounds on the \(H\) bus, so that (i) every two core-bus (or bus-core) CNOT gates in this gadget are separated by at least \(\alpha_{\mathsf{b}}\) level-0 SE rounds and (ii) transversal initialization and measurement are separated from the following and the preceding hybrid-unit CNOT gates, respectively, by at least \(\alpha_{\mathsf{b}}\) level-0 SE rounds. In addition, we require the layer of transversal \(H\) gates to be separated from any core-bus or bus-core CNOT gate by at least \(\alpha_{H}\) level-0 SE rounds. Here, \(\alpha_{H}\) is a new compilation parameter. For an even distance \(d_{0}\), since the core has asymmetrical \(X\) and \(Z\) boundaries (Fig. 4 (d)), the \(H\) bus after the transversal \(H\) gate is mismatched with cores along \(X\) boundaries (Fig. 17 (ab)). Therefore, now the \(H\) bus only supports bus-core CNOT gates with up to \(d_{1}-1\) cores at a time. This minor issue can be fixed by using an \(H\) bus of length \(d_{0}d_{1}+2\) (Fig. 17). For simplicity, we will not make such a modification to the bus length in what follows.

If \(x\cdot z\) is odd, there are two ways to measure \(\mathsf{P}_{xz}\). First, we can use a logical \(Y\) state as a catalyst to convert the logical measurement task back to the case above, where \(x\cdot z\) is even [40]. Suppose we reserve a single logical qubit in an HLP to host a logical \(Y\) state and we would like to perform the logical Pauli measurement \(\mathsf{P}_{xz}\) supported on other logical qubits. Then, we can instead measure \(\mathsf{P}_{xz}\cdot \overline{\mathsf{Y}}\) using the \(H\)-transformed logical readout gadget; here, \(\overline{\mathsf{Y}}\) is the logical \(Y\) operator corresponding to the logical \(Y\) state. In this way, we effectively measure \(\mathsf{P}_{xz}\) while preserving the logical \(Y\) state, which can be reused to assist future logical Pauli measurements. Alternatively, we can construct another readout gadget, called an \(HS\)-transformed readout gadget, to directly measure \(\mathsf{P}_{xz}\) without using ancillary logical states. The \(HS\)-transformed readout gadget works as follows.

• Same as steps 14 for the \(H\)-transformed readout gadget.

• Perform a level-1 \(S\) gate on the ancilla.

• Measure the ancilla in \(X\) basis.

The level-0 implementation of an \(HS\)-transformed readout gadget mostly follows from that of an \(H\)-transformed readout gadget. The only new step for the former is to perform a logical \(S\) gate on the \(H\) bus. Following the approach in Ref. [41], we can perform a mid-cycle fold-transversal \(S\) gate by leveraging the dynamics of the level-0 SE circuit on the bus [25], [41] (see Fig. 18). We require the mid-cycle transversal \(S\) gate to be separated from both the preceding bus-core CNOT gate and the final transversal \(X\)-basis measurement by at least \(\alpha_{\mathsf{b}}\) level-0 SE rounds.

We note that the level-0 implementation of both \(H\)-transformed and \(HS\)-transformed readout gadgets requires numerical benchmarking to optimize the number of padding level-0 SE rounds required between two adjacent logical operations on an \(H\) bus. We leave this to future work. In the remainder of this subsection, we theoretically analyze circuits with \(H\)-transformed readout gadgets (in addition to \(X\)-basis and \(Z\)-basis readout gadgets) under the phenomenological depolarizing noise model. We will extend Theorem 2 to prove that level-1 \(X\) (or \(Z\)) errors are almost uncorrelated even in the presence of \(H\)-transformed gadgets. Based on this result, we then formulate and analyze an LMS based on \(H\)-transformed gadgets to reliably measure a logical operator \(\mathsf{P}_{xz}\) with \(x\cdot z=0\). (The case \(x\cdot z=1\) can also be handled by such an LMS, given a logical \(Y\) state.)

Consider a level-0 circuit consisting of \(X\)-basis, \(Z\)-basis, and \(H\)-transformed readout gadgets, together with level-0 SE rounds on all working units. As described in Sec. 1.6, we partition level-0 detectors on cores and shuttle buses in \(X\)-basis and \(Z\)-basis readout gadgets into \(\mathcal{D}_{\mathsf{B}_{\lozenge}}\), \(\mathcal{D}_{\mathsf{C}}\), and \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\) and primitive level-0 \(X\) and \(Z\) errors on these working units into \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\), \(\mathcal{E}_{\mathsf{C}}\), and \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\). Since an \(H\) bus behaves similarly to an \(X\) or \(Z\) bus, we likewise partition the level-0 detectors on \(H\) buses into \(\mathcal{D}_{\mathsf{B}_{\lozenge}}\) and \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\), and the primitive level-0 \(X\) and \(Z\) errors on these buses into \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\) and \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\).

For an \(H\) bus \(\sigma\) in an \(H\)-transformed gadget, let \(t_{H}\) be the level-0 time step containing the transversal \(H\) gate on \(\sigma\). Construction of level-0 detectors on \(\sigma\) before (or after) time step \(t_{H}\) is the same as that on a \(Z\) bus (or an \(X\) bus). Every level-0 detector generated at time step \(t_{H}\) consists of the measurement result on a \(Z\) or \(X\) stabilizer in time step \(t_{H}-1\) and the measurement result on the corresponding \(X\) or \(Z\) stabilizer in time step \(t_{H}\). We refer to a level-0 detector on the bus as upstream (or downstream) if it is supported on \(X\) (or \(Z\)) stabilizer measurements before time step \(t_H\) and \(Z\) (or \(X\)) stabilizer measurements at or after time step \(t_{H}\). We refer to primitive qubit \(Z\) (or \(X\)) errors at or before time step \(t_{H}\), \(X\) (or \(Z\)) stabilizer measurement errors before time step \(t_{H}\), qubit \(X\) (or \(Z\)) errors after time step \(t_{H}\), and \(Z\) (or \(X\)) stabilizer measurement errors at or after time step \(t_{H}\) as upstream (or downstream) errors. Then, we add all upstream and downstream level-0 detectors on \(H\) buses to \(\mathcal{D}_{\mathsf{B}_{\lozenge}}\) and \(\mathcal{D}_{\mathsf{B}_{\blacklozenge}}\), respectively; we add all upstream and downstream level-0 errors on these buses to \(\mathcal{E}_{\mathsf{B}_{\lozenge}}\) and \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\), respectively. We can then construct all three level-0 decoding graphs and perform level-0 decoding according to Sec. 1.6. Define the upstream (or downstream) decoding subgraph on an \(H\) bus \(\sigma\) as the subgraph of \(\mathcal{G}_{\mathsf{B}_{\lozenge}}\) (or \(\mathcal{G}_{\mathsf{B}_{\blacklozenge}}\)) induced by the set of all upstream (or downstream) level-0 detectors on \(\sigma\).

We define the \(Z\)-basis (or \(X\)-basis) separation of an \(H\)-transformed readout gadget from another readout gadget as the minimum separation between a core-bus (or bus-core) CNOT gate in the \(H\)-transformed gadget and a core-bus (or bus-core) CNOT gate in the other. Suppose we are interested in a subset \(\mathcal{M}\) of readout gadgets, such that (i) \(X\)-basis (or \(Z\)-basis) readout gadgets in \(\mathcal{M}\) are separated by at least \(d_{0}\) level-0 time steps, and (ii) the \(X\)-basis and \(Z\)-basis separations of each \(H\)-transformed readout gadget in \(\mathcal{M}\) from any other readout gadget in \(\mathcal{M}\) are at least \(d_{0}\) level-0 time steps. Following notations in Sec. 2, we let \(\mathcal{E}_{\mathsf{B}_{\blacktriangledown}}\) be the subcollection of all level-0 errors in \(\mathcal{E}_{\mathsf{B}_{\blacklozenge}}\) on buses in \(\mathcal{M}\).

Consider a general level-0 residual error configuration \(f\). We know that \(f|_{\mathsf{B}_{\lozenge}}:=f_X|_{\mathsf{B}_{\lozenge}}\cup f_{Z}|_{\mathsf{B}_{\lozenge}}\) is a collection of \(X\)-basis cycles on \(X\) buses, \(Z\)-basis cycles on \(Z\) buses, and cycles on the upstream decoding subgraphs on \(H\) buses. We restrict all cycles in \(f|_{\mathsf{B}_{\lozenge}}\) to have a weight smaller than \(d_{0}d_{1}\) as we did in Sec. 2.2. Then, every cross-membrane cycle in \(f|_{\mathsf{B}_{\lozenge}}\) on an \(H\) bus is either an \(X\)-basis or \(Z\)-basis cycle. Let \(f^{\circ}\) denote the collection of propagated simple walks (on cores) from cycles in \(f|_{\mathsf{B}_{\lozenge}}\); let \(f_X^{\circ}\) (or \(f_{Z}^{\circ}\)) denote the collection of propagated simple walks (on cores) from \(X\)-basis (or \(Z\)-basis) cycles in \(f|_{\mathsf{B}_{\lozenge}}\). Then, \(f^{\circ}=f_{X}^{\circ}\cup f_{Z}^{\circ}\). Following Sec. 2.2, \(f_{X}^{\circ}\cup f_{X}|_{\mathsf{C}}\) is a disjoint union of \(X\)-basis closed walks on cores, such that each closed walk consists of propagated simple walks in \(f_{X}^{\circ}\) and length-1 walks (primitive level-0 errors) in \(f_{X}|_{\mathsf{C}}\). Let \(f_{X}^{\bullet}\) denote the propagated simple walks on buses in \(\mathcal{M}\) from these closed walks; we similarly define \(f_{Z}^{\bullet}\) as the propagated simple walks on buses in \(\mathcal{M}\) from \(f_{Z}^{\circ}\cup f_{Z}|_{\mathsf{C}}\).

Restricted to \(X\) (or \(Z\)) buses, \(f_Z^{\bullet}\cup f_{Z}|_{\mathsf{B}_{\blacktriangledown}}\) (or \(f_{X}^{\bullet}\cup f_{X}|_{\mathsf{B}_{\blacktriangledown}}\)) is a disjoint union of \(Z\)-basis (or \(X\)-basis) closed walks, potentially triggering readout errors on \(X\)-basis (or \(Z\)-basis) readout gadgets. However, restricted to the downstream decoding subgraph of an \(H\) bus, a closed walk may contain both \(X\)-basis walks in \(f_{X}^{\bullet}\cup f_{X}|_{\mathsf{B}_{\blacktriangledown}}\) and \(Z\)-basis walks in \(f_{Z}^{\bullet}\cup f_{Z}|_{\mathsf{B}_{\blacktriangledown}}\). In other words, restricted to \(H\) buses, \(f_{X}^{\bullet}\cup f_{X}|_{\mathsf{B}_{\blacktriangledown}}\cup f_{Z}^{\bullet}\cup f_{Z}|_{\mathsf{B}_{\blacktriangledown}}\) is a disjoint union of closed walks on downstream decoding subgraphs. We will choose the compilation parameter \(\alpha_{H}\) sufficiently large that closed walks containing walks from both \(f_{Z}^{\bullet}\) and \(f_X|_{\mathsf{B}_{\blacktriangledown}}\), or from both \(f_X^{\bullet}\) and \(f_{Z}|_{\mathsf{B}_{\blacktriangledown}}\), are strongly suppressed.

We assign two level-1 error locations during the lifetime of an \(H\) bus: a level-1 \(X\) error location (before the transversal \(H\) gate) and a level-1 \(Z\) error location (after the transversal \(H\) gate). Both error locations trigger the same readout error on the corresponding \(H\)-transformed readout gadget. Similar to Def. 4, we define the receptive zones for both error locations.

We generalize the definition of downstream webs (Def. 3). Let \(\{l_{1},\cdots,l_u\}\) be the collection of disjoint closed walks such that their union is \(f_{X}^{\bullet}\cup f_{X}|_{\mathsf{B}_{\blacktriangledown}}\cup f_{Z}^{\bullet}\cup f_{Z}|_{\mathsf{B}_{\blacktriangledown}}\). Consider two \(X\)-basis closed walks \(\ell_{1}\) and \(\ell_{2}\) as subsets of \(f_X^{\circ}\cup f_{X}|_{\mathsf{C}}\) on cores. Let \(\ell_{1}^{\bullet}\) and \(\ell_{2}^{\bullet}\) be the collections of propagated simple walks from \(\ell_{1}\) and \(\ell_{2}\), respectively. We say \(\ell_1\) and \(\ell_2\) are linked if there is a propagated simple walk in \(\ell_1^{\bullet}\) and another propagated simple walk in \(\ell_{2}^{\bullet}\) that belong to the same closed walk in \(\{l_1,\cdots,l_u\}\). Consider a set \(w\) consisting of closed walks on cores and native walks in \(f_{X}|_{\mathsf{B}_{\blacktriangledown}}\cup f_{Z}|_{\mathsf{B}_{\blacktriangledown}}\), such that (i) \(w|_{\mathsf{C}}\subset f_X^{\circ}\cup f_{X}|_{\mathsf{C}}\), (ii) \(w|_{\mathsf{B}_{\blacktriangledown}}\subset f_X|_{\mathsf{B}_{\blacktriangledown}}\cup f_Z|_{\mathsf{B}_{\blacktriangledown}}\) and contains no native closed walk, and (iii) \(\partial_{\blacktriangledown}w=0\). We say \(w\) is a generalized downstream fault web if \(w|_{\mathsf{C}}\) is a linked cluster of closed walks on cores.

We now extend Lemma 8 to bound \(f\) under certain additional restrictions. We follow the notation in Sec. 2.2, where the section map \(\mathbb{S}_{f}\) is defined, and the subscript \(\epsilon\) for a general level-0 error configuration denotes its physical-error component.

We now state and provide the following theorem, which extends Theorem 2 to incorporate \(H\)-transformed gadgets.

We note that we have not optimized for a larger threshold value in the above corollary. We only aimed to prove that for a small enough error rate \(p\), except for a rare event with probability \(\sim p^{-d_{0}d_1/2}\), the induced level-1 \(X\) (or \(Z\)) errors are effectively uncorrelated with a level-1 error rate \(\sim p^{-d_{0}/2}\). This result then aligns with Theorem 2.

We now construct an LMS, referred to as an \(H\)-LMS, from \(H\)-transformed logical readout gadgets to reliably measure a logical operator \(\mathsf{P}_{xz}\) with \(x\cdot z=0\). We note that the level-1 decoding process for a single \(H\)-LMS simultaneously involves level-1 \(X\) and \(Z\) errors. However, Corollary 1 only proves that the level-1 \(X\) (or \(Z\)) errors are almost uncorrelated but does not rule out correlation between level-1 \(X\) and \(Z\) errors. In practice, it is empirically observed that logical \(X\) and \(Z\) errors on an idling RSC are almost uncorrelated [1]. Thus, we may expect that we can effectively regard level-1 \(X\) and \(Z\) errors in an HLP as uncorrelated. Under this assumption, the \(H\)-LMS only requires \(d_{1}\) logical readout gadgets to achieve full level-1 distance. We note that future numerical benchmarking is required to substantiate this.

To guarantee the worst-case performance, we show in the following that an \(H\)-LMS, now consisting of \(4d_{1}\) logical readout gadgets across \(4d_1\) consecutive level-1 SE rounds, can reach similar logical performance even without the assumption above. We will use a modified level-1 decoding procedure (Algorithm 19). Based on this decoding procedure, we analyze the performance of this LMS without the above assumption.

From the above corollary that upper bounds the probability of logical measurement error for a single \(H\)-LMS, we can follow Theorem 3 to bound the probability of logical measurement errors for multiple LMSs (possibly including \(X\)-basis LMSs, \(Z\)-basis LMSs, and \(H\)-LMSs) on an HLP. We omit the exact error bound computation for brevity.

3.3 Extension module II: interfacing with external cores↩︎

As shown in Fig. 3 (f), we can perform a transversal CNOT gate with an external core (a distance-\(d_{ext}\) RSC with \(d_{0}\leq d_{ext}\leq d_{0}d_{1}\)) as the control and a \(Z\) bus as the target. We call such a gate an extended core-bus CNOT gate. Similarly, we can perform an extended bus-core CNOT gate between an \(X\) bus and an external core. Equipped with these extended hybrid-unit CNOT gates, the previously developed readout gadgets can jointly measure logical qubits on an HLP and on external cores. Note that we only allow external cores to directly interact with shuttle buses but not internal cores, therefore errors on external cores do not propagate to internal cores. Consider a simple setting where external cores are only allowed to interact with an HLP via readout gadgets but not with other external cores. Then, level-0 circuits on external cores have the same structure as those on internal cores. In this way, we can apply the arguments in Sec. 2 and Sec. 3.2 to bound level-1 error rates and the probability of logical measurement errors for LMSs in the presence of external cores. By analogy with Theorem 2 and Corollary 1, we expect that (i) level-1 \(X\) (or \(Z\)) errors are still local stochastic, (ii) the level-1 error rate on internal cores and shuttle buses scales as \(\sim p^{d_{0}/2}\), and (iii) the level-1 error rate on external cores scales as \(\sim p^{d_{ext}/2}\). Similarly, by analogy with Theorem 3 and Corollary 2, we expect the probability of logical measurement errors to be upper bounded by both \(\sim p^{d_{ext}/2}\) and \(\sim p^{d_{0}d_{1}/4}\). More generally, consider a hybrid architecture consisting of HLPs and external cores. Each HLP can perform its own logical Clifford operations with previously introduced LMSs and simultaneously interface with a subcollection of external cores. External cores that are currently not interfacing with any HLP can prepare special logical states (such as magic states) and participate in transversal logical Clifford gates. In this way, HLPs and external cores can collaborate to execute logical quantum computation (Fig. 20). We leave a careful theoretical and numerical analysis of this hybrid architecture for future work.

4 Numerical Simulation↩︎

In this section, we present concrete HLP designs and provide details of numerical simulations and performance extrapolation.

4.1 Details on HLP constructions and circuit-level simulation↩︎

As described in the main text, we can either use one shuttle bus at a time (Fig. 21) or two shuttle buses concurrently to implement the level-1 SE for an HLP based on the Iceberg code. For a \([[n^2,n-4n+2,4]]\) Square Berg code (\(n\) is divisible by 4) [1], we measure \(4n\) stabilizers in each level-1 SE round. As shown in Fig. 2 (a), among these stabilizers, there is one \(X\) stabilizer and one \(Z\) stabilizer associated with each row and each column. To perform a round of level-1 SE on an HLP based on a Square Berg code, we can use \(n\) shuttle buses at a time to measure the \(Z\) stabilizers of all columns, followed by \(X\) stabilizers of all columns, \(Z\) stabilizers of all rows, and finally \(X\) stabilizers of all rows. We use this level-1 SE design for the two HLPs based on the \([[64,34,4]]\) and \([[256,194,4]]\) Square Berg codes in Fig. 2.

For simulating logical memories with perfect time boundaries, we follow the approach in Ref. [1] to simultaneously detect logical \(X\) and \(Z\) errors. More specifically, for every logical qubit, we associate it with a perfect physical qubit, referred to as the register qubit. For each logical qubit \(i\), let \(\overline{\mathsf{X}}_{i}\) and \(X_i\) denote the logical \(X\) operator and the Pauli \(X\) operator on the associated register qubit, respectively. Similarly, let \(\overline{\mathsf{Z}}_{i}\) and \(Z_i\) be the logical \(Z\) operator and the Pauli \(Z\) operator on the register qubit, respectively. To perfectly initialize the logical memory, we first measure all (level-0 and level-1) stabilizers perfectly, then we measure \(\overline{\mathsf{X}}_{i}\otimes X_{i}\) and \(\overline{\mathsf{Z}}_{i}\otimes Z_{i}\) perfectly for every logical qubit \(i\), thereby effectively creating a Bell pair between every logical qubit and its register qubit. After initialization, register qubits are left idling without noise, while qubits and gates in logical memory are subject to circuit-level noise. Finally, we repeat the perfect measurement procedure used in initialization. In this way, both logical \(X\) and \(Z\) errors can be detected simultaneously. If the logical qubit \(i\) is initialized or measured by measuring both \(\overline{\mathsf{X}}_i\otimes X_i\) and \(\overline{\mathsf{Z}}_i\otimes Z_i\), then we say this logical qubit is initialized or measured in the Bell basis. On the other hand, if a logical qubit \(i\) is initialized or measured by measuring \(\overline{\mathsf{X}}_i\) (or \(\overline{\mathsf{Z}}_i\)), then we say this logical qubit is initialized or measured in the \(X\) (or \(Z\)) basis.

In Fig. 3 (c), we present circuit-level simulations for benchmarking logical Pauli \(Z\) measurements (implemented with LMSs) on an HLP based on the \([[8,6,2]]\) Iceberg code with compilation parameters \(\alpha_{\mathsf{c}}=1\) and \(\alpha_{\mathsf{b}}=0.5\). We simulated three circuits, all having perfect time boundaries and running the HLP for five level-1 SE rounds, where the level-1 \(X\) and \(Z\) stabilizers are measured sequentially, as in Fig. 21. The first is a memory baseline circuit with six logical qubits initialized and measured in the Bell basis. Here, each logical qubit \(i\in\{1,\cdots 6\}\) is assigned a logical \(X\) operator \(\overline{\mathsf{X}}_i=\mathsf{X}_{1}\otimes \mathsf{X}_{i+1}\) and a logical \(Z\) operator \(\overline{\mathsf{Z}}_i=\mathsf{Z}_{i+1}\otimes \mathsf{Z}_{8}\). The second and the third circuits contain one and three LMSs, respectively. Since the LMS in the second circuit exactly corresponds to one LMS in the third circuit, we elaborate on the latter in the following. As described in the main text, the three LMSs measure three logical \(Z\) operators: \(\overline{\mathsf{Z}}_1\otimes\cdots \otimes\overline{\mathsf{Z}}_6\), \(\overline{\mathsf{Z}}_{1}\otimes \overline{\mathsf{Z}}_2 \otimes \overline{\mathsf{Z}}_3\), and \(\overline{\mathsf{Z}}_4\otimes \overline{\mathsf{Z}}_5\otimes\overline{\mathsf{Z}}_6\), respectively. We define a new set of logical qubits with the following logical \(X\) and \(Z\) operators. \[\begin{array}{ll} \overline{\mathsf{Z}}'_1:=\overline{\mathsf{Z}}_1\otimes\cdots\otimes \overline{\mathsf{Z}}_{6}, & \overline{\mathsf{X}}_1':=\overline{\mathsf{X}}_{6}\\ \overline{\mathsf{Z}}'_2:=\overline{\mathsf{Z}}_1\otimes\overline{\mathsf{Z}}_2\otimes \overline{\mathsf{Z}}_{3}, & \overline{\mathsf{X}}_2':=\overline{\mathsf{X}}_1\otimes\overline{\mathsf{X}}_{6}\\ \overline{\mathsf{Z}}'_3:=\overline{\mathsf{Z}}_2, & \overline{\mathsf{X}}_3':=\overline{\mathsf{X}}_1\otimes\overline{\mathsf{X}}_{2}\\ \overline{\mathsf{Z}}'_4:=\overline{\mathsf{Z}}_3, & \overline{\mathsf{X}}_4':=\overline{\mathsf{X}}_1\otimes\overline{\mathsf{X}}_{3}\\ \overline{\mathsf{Z}}'_5:=\overline{\mathsf{Z}}_4, & \overline{\mathsf{X}}_5':=\overline{\mathsf{X}}_4\otimes\overline{\mathsf{X}}_{6}\\ \overline{\mathsf{Z}}'_6:=\overline{\mathsf{Z}}_5, & \overline{\mathsf{X}}_6':=\overline{\mathsf{X}}_5\otimes\overline{\mathsf{X}}_{6} \end{array}\] We initialize and finally measure the first two logical qubits in the \(Z\) basis and the remaining logical qubits in the Bell basis, such that (i) the LMS outcomes are predetermined by initialization and (ii) errors on logical degrees of freedom not measured by the LMSs can be detected. The two logical readout gadgets in each LMS are embedded in the third and fourth level-1 SE rounds, respectively. More specifically, each logical readout gadget is contained within the lifetime of an \(X\) bus for measuring the level-1 \(X\) stabilizer. The scheduling of three logical readout gadgets corresponding to the three LMSs inside a single level-1 SE round is shown in Fig. 22. We note one anomaly in the scheduling: a core-bus CNOT gate coupling the \(Z\) bus on the bottom of Fig. 22 to two cores is now split into two adjacent level-0 time steps to avoid multiple core-bus CNOT gates operating on the same core at the same time. This scheduling choice does not comply with the restrictions imposed in Sec. 1. However, these restrictions are primarily introduced to simplify the analysis and presentation rather than to represent hard architectural constraints; practical implementations generally provide additional scheduling degrees of freedom beyond those assumed in our analysis. The simulation results presented in Fig. 3 (c) further validate this point.

As mentioned in Sec. 1.6, we use correlated level-0 decoding in our circuit-level simulations. We extract soft outputs at the end of this procedure. We note that correlated level-0 decoding reduces to correlated matching [68] for an idling core.

4.2 Soft-output Simulation↩︎

In this subsection, we describe a high-speed heuristic sampling method, soft-output simulation, that directly simulates a level-1 circuit by sampling level-1 errors and then performing level-1 decoding. This method is essentially the gap simulation method developed in Ref. [1] with gap values replaced by soft outputs [39]. The level-1 circuit error model we use is more refined than the one in Ref. [1].

The soft-output simulation procedure is described in Algorithm 23, which requires two key ingredients. First, we need to efficiently construct the soft-output distribution for canonical segments with various lengths, Pauli basis, and working-unit types under different values of \(d_{0}\). Secondly, we need to construct the function \(\mathrm{LER}\) that infers the level-1 error probability for a canonical segment based on its soft output. We elaborate on these ingredients in the following.

Soft-output distributionWe first construct a reference soft-output distribution on core segments with a fixed length of \(10d_{0}\) for each core size \(d_{0}\in\{3,4,\cdots,12\}\). To achieve this, we perform circuit-level simulation of an idling circuit on a single core with \(10d_{0}\) level-0 SE rounds (Fig. 24 (a)). For each simulation shot, we extract a pair of soft outputs [39], one on the \(X\)-basis and one on the \(Z\)-basis segment, where both segments span all level-0 SE rounds. From these reference distributions, we can heuristically infer soft-output distributions for canonical segments on cores and shuttle buses [1]. Denote the soft-output distribution on an \(X\)-basis (or \(Z\)-basis) core segment with a length of \(t\) level-0 time steps and a core size \(d_{0}\) as \(P_{X,t,d_0}\) (or \(P_{Z,t,d_{0}}\)). Define the corresponding complementary cumulative distribution function (CCDF) \(\overline{F}_{A,t,d_{0}}\) (\(A\in\{X,Z\}\)) by \(\overline{F}_{A,t,d_0}(\phi):=\sum_{\phi'\geq\phi}P_{A,t,d_{0}}(\phi')\). Following Ref. [1], from our reference CCDF \(\overline{F}_{A,10d_{0},d_{0}}\) (obtained from the reference distribution above), we heuristically infer another CCDF \(\overline{F}_{A,t',d_{0}}\) corresponding to a segment length \(t'\) as \[\label{eq:32CCDF32inference} \overline{F}_{A,t',d_{0}}(\phi):=\left(\overline{F}_{A,10d_{0},d_{0}}(\phi)\right)^{\frac{t'}{10d_{0}}}.\tag{17}\] As a CCDF uniquely determines a distribution, we can obtain from Eq. 17 the soft-output distribution \(P_{A,t',d_{0}}\). Similarly, consider an \(X\) (or \(Z\)) bus with a width of \(d_{0}\) and a length of \(d_{0}d_{1}\). Denote the soft-output distribution on an \(X\)-basis (or \(Z\)-basis) segment with a length of \(t\) as \(P_{A,t,d_{0},d_{1}}\) with \(A=X\) (or \(A=Z\)); denote the corresponding CCDF as \(\overline{F}_{A,t,d_{0},d_{1}}\), which is inferred as \[\overline{F}_{A,t,d_{0},d_{1}}(\phi) := \left(\overline{F}_{A,10d_{0},d_{0}}(\phi)\right)^{\frac{td_1}{10d_{0}}}.\] We test the validity of this heuristic inference method by comparing the inferred soft-output distributions with the numerically sampled ones for the circuits in Fig. 24 (bd) and observe close agreement between the two (Fig. 24 (e)).

Level-1 error rate estimation from soft outputsWe use all sampling results for the core-idling circuit in Fig. 24 (a) with \(d_{0}\in\{3,\cdots,12\}\) to fit the following parametrized ansatz for estimating logical \(X\) (or \(Z\)) error rates from \(Z\)-basis (or \(X\)-basis) soft outputs: \[\label{eq:32ler32ansatz32for32soft32outputs} \mathrm{LER}_{a,b}(\phi):=\min(a\cdot 10^{-b\cdot\phi/10},0.5),\tag{18}\] where \(a\) and \(b\) are non-negative fitting parameters. We find that \(a=0.65\) and \(b=1\) provides a close fit for both logical \(X\) and \(Z\) error rates (Fig. 25 (a)). We compare this fitted ansatz with data pairs consisting of \(X\)-basis soft outputs and logical \(Z\) error rates on a core for circuits in Fig. 24 (b) and Fig. 24 (d). The fitted ansatz matches the data points well for the idling circuit in Fig. 24 (b), while data points for the circuit in Fig. 24 (d) containing core-bus CNOT gates exhibit some deviation at large soft output values for small \(d_{0}\)more specifically, logical \(Z\) error rates plateau at large soft output values. We attribute the deviation, at least in part, to logical \(Z\) errors on the \(Z\) bus between the two core-bus CNOT gates.

Soft outputs collected for the idling core (Fig. 24 (a)) also allow a fine-grained study of correlations between logical \(X\) and \(Z\) errors on the core. From these data, we obtain, for each core distance \(d_{0}\in\{3,\cdots,12\}\), both the joint distribution of \(X\)-basis and \(Z\)-basis soft outputs and the product of their marginal distributions. We observe close agreement between the joint distribution and the product distribution for all \(d_{0}\in\{4,\cdots,12\}\), indicating that the \(X\)-basis and \(Z\)-basis soft outputs are approximately independent. See Fig. 26 (ab) for an illustration of the \(d_{0}=7\) case. Since the \(X\)-basis and \(Z\)-basis soft outputs accurately predict probabilities for logical \(Z\) and \(X\) errors, respectively, this independence suggests that the logical error probability in one basis is insensitive to the component of physical-error configuration in the other basis, at the resolution captured by soft outputs. More specifically, we group physical-error configurations according to the \(Z\)-basis soft outputs determined by the \(X\)-basis components of those configurations. Across these groups, the logical \(Z\) error probability remains approximately unchanged. Conversely, we group physical-error configurations according to the \(X\)-basis soft outputs determined by the \(Z\)-basis components of those configurations. Across these groups, the logical \(X\) error probability remains approximately unchanged. Ref. [1] observed that the overall logical \(X\) and \(Z\) errors are approximately uncorrelated on an idling core. The fine-grained study above extends this observation to soft-output-conditioned logical error probabilities. As discussed in Sec. 3.2, if level-1 \(X\) and \(Z\) errors are uncorrelated, we expect an \(H\)-LMS with \(d_1\) \(H\)-transformed logical readout gadgets to achieve full level-1 distance. Without this assumption, Corollary 2 provides a worst-case guarantee for an \(H\)-LMS with \(4d_1\) such gadgets. The observation that level-1 \(X\) and \(Z\) errors on an idling core are approximately uncorrelated provides a starting point for future studies of correlations among level-1 \(X\) and \(Z\) errors on an HLP, as well as the optimization of \(H\)-transformed readout gadgets and \(H\)-LMSs.

As described in the main text (Fig. 2 (b)), we test the accuracy of soft-output simulation on the following two HLPs:

1. An HLP with the \([[4,2,2]]\) Iceberg code as the level-1 code. The HLP is run as a memory for ten level-1 SE rounds.

2. An HLP with the \([[64,34,4]]\) Square Berg code as the level-1 code. We simulate only five level-1 SE rounds on the HLP, since circuit-level simulation is costly at this scale.

As shown in Fig. 27, the soft-output simulations using the fitted level-1 error rate ansatz \(\mathrm{LER}_{0.65,1}\) produce results close to those obtained from circuit-level simulations. However, they consistently underestimate the logical error rates, and the gap grows slightly with increasing core distance \(d_{0}\). To reduce this dependence on \(d_{0}\), we use a slightly tuned ansatz \(\mathrm{LER}_{0.5,0.9}\), which yields slightly higher estimates of level-1 error rates than \(\mathrm{LER}_{0.65,1}\) at large soft-output values. With this ansatz, the gap between the soft-output and circuit-level simulations remains almost constant for both HLPs as \(d_{0}\) increases. We therefore use \(\mathrm{LER}_{0.5,0.9}\) for the soft-output simulations of the other HLPs in the following subsection. Moreover, to account for the remaining gap, we multiply the logical error rates obtained from the soft-output simulations by a factor of two when estimating the logical error rates of HLPs.

4.3 Extrapolation for logical error rates↩︎

In this subsection, we describe how we extrapolate the performance of the RSC and HLPs to obtain the qubit and time overhead estimation in Fig. 2 (cd). For the RSC, we perform circuit-level simulation of the idling circuit in Fig. 24 (a) with a correlated-matching decoder [68] and distance \(d_{0}\) ranging from \(3\) to \(10\). We fit the logical error rates (per SE round) as a function of the code distance to \(\mathrm{LER}_{\mathrm{RSC}}^{a,b}(d_{0})=a^{-d_{0}}/b\) (Fig. 28 (a)). For HLPs based on \([[n_1,n_1-2,2]]\) Iceberg codes with a single shuttle bus operating at a time, we use soft-output simulation (of \(10\) level-1 SE rounds) to estimate their logical error rates for code sizes \(n_1\in\{4,8,12\}\) and core distance \(d_{0}\) ranging from \(3\) to \(7\) (Fig. 28 (b)). Using data with \(d_{0}\in\{5,6,7\}\), we fit the logical error rates per level-1 SE round to \(\mathrm{LER}_{\mathrm{ICE}}^{a,b,c}(d_{0},n_1,r)=r^{c}\cdot n_1^2\cdot a^{-d_{0}}/b\), where \(r\) is the length of each level-1 SE round [1]. We expect the fitted parameter \(c\) to be close to the Iceberg-code distance [1]. Similarly, we use soft-output simulation to study HLPs based on Iceberg codes with two shuttle buses operating concurrently, and perform the same procedure described above (Fig. 28 (b)). For HLPs based on the \([[256,194,4]]\) Square Berg code with different numbers of concurrent shuttle buses, we perform soft-output simulation of 10 level-1 SE rounds and use the data with \(d_{0}\in\{5,6,7\}\) to fit the logical error rates per level-1 SE round to \(\mathrm{LER}_{\mathrm{SQR}}^{a,b,c}(d_{0},r)=r^{c}\cdot a^{-d_{0}}/b\) (Fig. 28 (c)). Based on these fitted logical error rate ansatzes, we can determine the core distance \(d_{0}\) required to attain a target logical error rate. This then allows us to estimate the qubit overhead per logical qubit and time overhead per level-1 SE round.

References↩︎