1 Introduction↩︎

Artificial Intelligence (AI) based on Deep Neural Networks (DNNs) has achieved remarkable cognitive capability across diverse domains, including language processing, computer vision, autonomous driving, and healthcare [1]–[4]. These advances are accompanied by an exponential growth in compute complexity and input/model size, imposing an ever-increasing demand for heavy computing resources. At present, graphics processing units (GPUs) with high-bandwidth memory (HBM) are the major workhorses fueling AI computation, thanks to their massive processing parallelism [5] combined with specialized high memory bandwidth. However, building large-scale AI data centers based on the power-hungry GPU+HBM platforms has created an immense challenge for the underlying energy infrastructure. It has been projected that data center workload will make up 30-40 percent of all new energy demand in the United States by 2030 [6]. Therefore, the rapid growth of data center energy consumption has become a societal and environmental concern, motivating the exploration of the unconventional deployment of AI data centers in environments where abundant energy can be harnessed at scale.

Space (orbital) data centers have recently emerged as a promising solution to the future scaling of AI compute infrastructure, thanks to the immense potential of the continuous and high-intensity solar energy source and virtually unlimited physical room for large-scale deployments [7]. However, while the cold background temperature in space may seem attractive for keeping the compute chips cool, AI platforms working in the space vacuum must operate without convection. As a result, cooling becomes a critical challenge for space computing infrastructure as chips must rely ultimately on thermal radiation for heat exchange with the surrounding [8]. Unlike convection-based cooling on earth, where small heat sinks can reject substantial heat, radiative cooling demands large and heavy radiators, severely constraining the operating power of the supported AI compute systems. The volume and mass of radiators now become crucial for designing space computing systems.

Standard terrestrial GPUs typically rely on a combination of liquid and fan cooling to reach near-peak performance while maintaining a safe working temperature [9]. Hence, if deployed in space, the severe thermal constraints will inevitably impact the computational performance of standard GPU+HBM systems. It is important to note that the majority of the energy consumption with GPUs is attributed to the data movement between HBM and the GPU compute logic [10], commonly known as the von Neumann memory wall bottleneck. To tackle the issues of heat generation and concentration in GPU+HBM systems, compute-in-memory (CIM) architecture with various memory technologies has been extensively investigated to seek an alternative pathway to compute efficiency[11]. In particular, CIM accelerators based on non-volatile memory (NVM) offer high on-chip memory density and low static power, suggesting immense potential for inference acceleration. While most research on CIM focuses on demonstrating energy-efficiency improvements for AI computation, it remains largely unexplored how these CIM systems perform under passive thermal constraints (such as given a radiator rejection power budget).

In this work, we systematically investigate how CIM accelerators perform in comparison with standard GPU+HBM under realistic cooling constraints bounded by the availability of radiators. We demonstrate that crossbar-based CIM architectures mitigate the memory bottleneck and manage to both (1) achieve improved power efficiency and (2) eliminate the thermal hotspots. To the best of our knowledge, our work is the first design exploration of CIM accelerators for space computing with radiator constraints in the loop. The major contributions of the paper are the following:

• We conduct finite-element-methods (FEM)-based system modeling to assess the impact of limited cooling on AI hardware in space. Under the iso-chip-area condition with fixed radiator thermal rejection power, the compute-efficient CIM results in lower overall chip temperature. Interestingly, compared to GPU+HBM systems that exhibit strong thermal hotspots, CIM accelerators exhibit a homogeneous spatial thermal profile, thereby eliminating the hotspot issue.

• A radiator-in-the-loop thermal-electronic co-design methodology is developed for optimizing CIM architecture for thermally constrained space platforms. Concretely, we propose an evaluation framework based on a roofline-like modeling that explicitly links radiator availability to the impact of thermal throttling on peak performance. The performance improvement of CIM over standard GPU systems is quantified based on the proposed modeling framework.

• Various CIM architectural configurations are evaluated for a diverse group of representative AI compute workloads. Our system evaluation based on the thermal-aware roofline modeling demonstrates that CIM accelerators consistently deliver over 10-40x improvement in TOPS compared to GPU+HBM under tight thermal constraints. The magnified performance advantage of CIM over GPU opens up an exciting venue for developing AI hardware for space computing.

2 Related Works↩︎

2.1 Thermal Management for AI Hardware↩︎

Cooling is a key design concern for large-scale computing infrastructure. Advanced thermal management packaging cools chips in terrestrial environments, and liquid and air cooling are combined in state-of-the-art data centers[12], [13]. Beyond rapid heat removal, thermal management must address thermal coupling between on-chip components under non-uniform heat generation. In conventional GPU+HBM systems (e.g., GPU A100), most power is concentrated on the GPU die, creating high-power-density hotspots[14]. Thermal coupling between the GPU and temperature-sensitive HBM dies triggers throttling and lowers effective throughput below peak[15]. Dynamic Voltage and Frequency Scaling (DVFS), the standard GPU power management technique, balances performance, power, and heat as a reactive safeguard against overheating[16], [17]. As detailed later, our analysis shows that both total heat and non-uniform spatial thermal profiles are harder to manage in space, causing significant performance degradation for standard GPUs on space platforms.

2.2 Space AI Compute↩︎

Space AI compute is drawing growing academic and industrial interest, enabled by continuous solar power without weather losses and the possibility of passive radiative cooling to vacuum. As technologies mature, space compute will first support onboard processing of satellite and orbital sensor data (e.g., remote sensing, telescope imaging), then progress toward full data-center-class AI compute in low Earth orbit (LEO). Though nascent, the field has already achieved milestones, including the first in-space use of an H100 GPU [18] to run intermediate-size AI workloads such as nanoGPT training [19].

Major challenges remain for large-scale deployment, notably thermal management without convection and ensuring electronics reliability under intense cosmic radiation. Radiation-hardening techniques from space and mission-critical electronics can protect AI hardware [20], and recent radiation-tolerance tests on Google TPUs show promising accelerator resilience [21]. Additional challenges span the deployment life cycle, including launch costs, SWaP (Size, Weight, and Power) constraints, inter-satellite and satellite– ground communication, and maintenance logistics. This work focuses on the thermal constraint and proposes a hardware solution.

2.3 Compute-In-Memory Accelerators↩︎

To overcome the von Neumann memory bottleneck in standard digital hardware, memory-centric architectures bring memory and compute units together (“in-memory”) or near each other (“near-memory”) [23]. Crossbar-based Compute-In-Memory (CIM) with analog accumulation is a promising AI acceleration paradigm: it performs MAC operations within memory cells and uses Kirchhoff’s law across columns for analog accumulation, enabling massively parallel, in-situ matrix-vector multiplications (MVM) with greatly reduced data movement [11]. Experiments show that crossbar CIM can effectively mitigate the memory wall and potentially surpass GPU+HBM systems in energy efficiency, measured in terms of Trillion Operations Per Second per Watt (TOPS/W) [24], [25]. CIM also yields a more uniform spatial heat distribution by spreading matrix-vector workloads across memory arrays [26], eliminating hotspots seen in HBM+GPU systems. As detailed later, our evaluation shows that CIM systems not only generate less total heat due to higher energy efficiency, but also alleviate thermal hotspots under tight power and thermal constraints.

3 Thermal Characterization of AI accelerators↩︎

Thermal modeling setup. We characterize the thermal behavior of GPU+HBM and CIM-based AI accelerators under varying operating and cooling conditions. Using Comsol [27], we model GPU, HBM, and CIM package components and run finite element method (FEM) solid heat-transfer simulations. The goal is to accurately evaluate temperature distribution under different power levels and radiator thermal rejection power (TRP) budgets. The GPU core is modeled as a monolithic silicon (Si) die. The HBM is modeled stack-wise, including the physical I/O on the logic die (Logic-PHY), through-silicon vias (TSVs) connecting the logic layer (Logic-TSV) and DRAM layers (DRAM-TSV), and DRAM banks, following [14]. HBM dimensions and power distribution are scaled to an 8-Hi stack configuration with six stacks at a combined 80 W and 1.9 TB/s bandwidth [10], matching an NVIDIA A100-class GPU+HBM system at 400 W and 624 TOPS [9]. The full GPU+HBM package is placed on a silicon interposer with Si dies for DRAM and Logic-PHY and \(SiO_2\)-encased Cu TSVs. The CIM system is modeled as four Si chips on a silicon interposer with a form factor similar to the A100-like GPU+HBM system. Component area and power are estimated using CiMLoop [22] with parameters from [26], summarized in Table 1. Memory cell/array configurations and the peripheral circuits for analog-digital converters (ADC) will be varied for CIM design-space exploration. The radiator is modeled as a flat panel rejecting \(100~W/mm^2\) [28] at 85 °C.

Comparison of thermal maps. Fig. 2 shows thermal maps for GPU+HBM and a representative CIM system at 195 W, 200 W, and 205 W under a fixed 200 W TRP. In GPU+HBM systems, the GPU core has the highest power density and dominates heat generation, quickly reaching high temperatures even within the TRP budget, while thermal coupling raises temperatures in the thermally sensitive HBM stacks. In contrast, CIM systems avoid high power-density hotspots, yielding a more uniform thermal profile and safe operation within TRP limits.

The GPU+HBM system consistently shows a severe hotspot at the GPU core. While total power stays within the TRP limit, hotspot severity increases with power, indicated by a growing temperature gap across chip regions. In contrast, the CIM system sustains lower average temperatures and an almost uniform thermal profile; simulations show that CIM eliminates hotspots even at higher power.

Quantification of elevated temperature. High power density and thermal coupling push both the GPU core and HBM above safe temperatures under nominal TRP. The GPU core must throttle when the logic die exceeds 95 °C. Elevated HBM temperatures increase refresh rates, cutting effective bandwidth to about 73% at 85 °C [29]. Fig. 3 (a) shows that, even at the limited TRP, GPU core and HBM exceed safe limits, requiring system-level power reduction to maintain reliability.

Power density analysis. We analyze power density across GPU+HBM and CIM components. The GPU+HBM system includes high-density regions such as the GPU-core and Logic-PHY, while the CIM system comprises RRAM crossbar arrays, row drivers, ADCs, digital units, NoC (network on chip interconnects), and buffers. As shown in Fig. 3 (b), the GPU-core and Logic-PHY have much higher power densities than other components, whereas CIM components remain low and nearly uniform. Fig. 3 (b) also shows GPU-core power density under different DVFS operating points, along with two TRP capacity levels indicating power density headroom. The GPU-core must greatly reduce its operating frequency to operate safely within TRP constraints.

Particularly, more than 50% clock frequency reduction is needed to accommodate a TRP of 200 W.

4 Evaluation Methodology↩︎

We develop a thermal-aware hardware simulation framework to evaluate the performance of GPU+HBM and different CIM configurations under space thermal constraints. In space environments, AI accelerators rely entirely on radiative cooling for safe operation. Based on the Stefan-Boltzmann law, \(P_{rad} = \epsilon \cdot \sigma \cdot A \cdot (T^4 -T_{ext}^4)\), the radiator area and material emissivity \(\epsilon\) determine the maximum thermal power that can be dissipated at a given operating temperature (\(T\)) and external temperature (\(T_{ext}\)). The external temperature \(T_{ext}\) is set at \(140~K\) as a low end for the temperature range of near-earth orbits [30], which is negligible compared to the operating temperature of 85 °C. For our experiments, we conservatively assume a radiator thermal rejection capability of 100 \(W/m^2\) [28], making radiator area and TRP the primary thermal constraints.

DVFS performance scaling. To operate GPU+HBM and CIM configurations under different TRP (or radiator area) constraints, dynamic voltage-frequency scaling (DVFS) is applied. Under DVFS, system power scales with voltage (\(V\)) and frequency (\(f\)) as \(P \propto C \cdot V^2 \cdot f\), which can be approximated as \(P \propto f^\alpha\) based on the \(V\)–\(f\) relationship. In modern GPUs, voltage remains approximately constant at low frequencies and scales linearly with frequency at higher operating points [16], [31]. Using empirical power–frequency data from [31], we model this behavior with \(\alpha = 1\) for \(f < f_{breakpoint}\) and \(\alpha = 2.1\) for \(f \geq f_{breakpoint}\).

Thermal-aware CIM design. The DVFS model for CIM systems follows a simpler relationship due to the presence of mixed-signal peripheral components. We assume a fixed operating voltage across the frequency range, resulting in \(P \propto f\). Based on these DVFS models, we estimate the achievable performance (TOPS) under given TRP constraints. Fig. 4 illustrates the workflow for thermally-aware

CIM design space exploration, considering varying thermal constraints, workload characteristics, and hardware parameters such as crossbar array configurations and peripheral designs. As established in Sec. 3, CIM systems avoid thermal hotspots under power constraints, enabling efficient exploration of achievable TOPS within the radiator-limited design space.

5 Results and Discussion↩︎

Experimental setup. We perform thermal-aware CIM design space exploration based on an ISAAC-like [26] CIM architecture with multiple configurations under varying space radiator thermal rejection power limits. The CIM systems are simulated using CiMLoop, a fast design-space exploration framework for CIM architectures [22], targeting a 16nm technology node. All comparisons are conducted under iso-area constraints. Specifically, the CIM system consists of four chips, each of 625 \(mm^2\), integrated on a silicon interposer with a total form factor of  2700 \(mm^2\).

We compare these configurations against an NVIDIA A100 GPU+ HBM system, labeled as GPU. The A100 operates at a peak power of 400 W at 1.4 GHz (\(f_{max-GPU}\)) and a minimum power of 100 W at 165 MHz (\(f_{min-GPU}\)), following the DVFS model described in Sec. 4. Based on empirical observations [31], the breakpoint frequency (\(f_{breakpoint}\)) is estimated as 1.1 GHz. The HBM subsystem operates at 80 W and delivers 1.9 TB/s bandwidth [10], while the GPU achieves 624 TOPS for 8-bit operations [9]. As for the static power consumption, approximately 60 W (about 15% of peak power) is for a standard 400W GPU, while non-volatile-memory-based CIM systems have a reduced static power percentage at 5%. The CIM configurations operate over a frequency range of 8 MHz (\(f_{min-CIM}\)) to 20 MHz (\(f_{max-CIM}\)), accounting for the peripheral ADC and the delay of the resistive crossbar array. Additionally, DDR5 DRAM is considered as off-chip memory for CIM, operating at 60 W and providing

536 GB/s bandwidth [32]. All evaluations assume 8-bit-precision weights/activations. The experimental system and device parameters are summarized in Table 2

Performance comparison under varying TRP. We compare three representative CIM configurations with the GPU under varying TRP budgets. These include resistive RAM (RRAM) with 1-bit and 2-bit per cell (R_ON/R_OFF = 100k/1M\(\Omega\)) [33], labeled as RRAM-1b/2b, and spin-transfer torque MRAM (STT-MRAM) with 1-bit per cell (R_ON/R_OFF = 13k/26k\(\Omega\)) [35], labeled as STT-MRAM-1b. All CIM standard configurations employ 128\(\times\)​128 crossbar arrays with 4-bit ADCs.

As shown in Fig. 5 (a), CIM systems consistently achieve higher effective TOPS than the GPU across a wide range of TRP budgets, primarily due to their superior TOPS/W efficiency. All systems cease operation if the TRP constraint forces them below their minimum operating frequency (\(f_{min}\)). Notably, RRAM-based CIM configurations continue to operate under extremely low power budgets where the GPU must shut down. At the upper end, once systems reach their maximum frequency (\(f_{max}\)), additional radiator capacity only reduces temperature without improving TOPS. Fig. 5 (b) summarizes normalized performance, showing that CIM systems can achieve up to \(\sim\)​40\(\times\) higher TOPS than the GPU under stringent radiator constraints (e.g., \(1~m^2\) radiator at 100 \(W/m^2\)). Although the GPU can partially close this gap at higher TRP budgets due to higher achievable clock frequencies, CIM systems maintain overall performance advantages.

CIM design exploration. We evaluate variations in RRAM-based CIM under a constrained TRP budget of 100 W (1 \(m^2\) radiator @ 100 \(W/m^2\)). The explored parameters include the number of array rows (Row), columns per ADC (Col), ADC resolution (ADC), bits per cell (BpC), and on-state resistance (ROn). Each design point varies a single parameter while keeping a baseline configuration of [Row=128, Col=128, ADC=4, BpC=1, ROn=100k\(\Omega\)]. As shown in Fig. 6, all CIM configurations outperform the GPU, with the best performance achieved with low-bit ADC and multiple bits/cell. It is important to note that the ADC precision will be bounded by the accuracy requirement and 2-4 bits ADC for 128x128 array have been shown feasible [36].

Workload-level comparison. Finally, we evaluate representative CIM systems (RRAM-1b/2b and STT-MRAM-1b) and the GPU+HBM system across diverse workloads. Fig. 7 (a) presents roofline models for the GPU and a representative CIM configuration (RRAM-1b) under radiator budgets of 1 \(m^2\) (left) and 3 \(m^2\) (right). The workloads include General Matrix Multiplication between two (\(N \times N\)) matrices (GEMM-N), where N = 128 and 4096 (GEMM-128 and GEMM-4096), as well as Large Language Model (LLM) tasks. The LLM workloads are denoted as LM-pf/dc-x-y, where LM refers to the Llama-3.2-3B model [37], pf and dc denote the Prefill and Decode phases, and x, y represent batch size and sequence length, respectively.

The results show that CIM systems achieve higher operational intensity due to weight-stationary dataflow and maintain superior TOPS under radiator constraints, outperforming the GPU across most workloads. Fig. 7 (b) summarizes normalized performance across representative workloads, including small (S) and large (L) configurations: GEMM-S/L (128/4096), LM-pf/dc-S (LM-pf/dc-1-512), and LM-pf/dc-L (LM-pf/dc-16-2048). Under tight radiator constraints (1 \(m^2\)), CIM systems significantly outperform the GPU across all workloads. With increased radiator area (3 \(m^2\)), the GPU reduces the performance gap due to its higher clock frequency and HBM bandwidth, but CIM configurations continue to provide competitive or superior performance.

6 Conclusion↩︎

We demonstrate the potential of deploying NVM-based CIM accelerators in space under strict radiator-only cooling constraints. We show that conventional GPU+HBM systems suffer from high-power-density hotspots and thermal throttling, constraining performance under limited radiator capacity. In contrast, CIM achieves higher TOPS/W performance thanks to the inherently reduced data movement and uniform power distribution. Our results demonstrate that CIM accelerators consistently deliver over 10-40\(\times\) higher effective TOPS than GPU+HBM under tight radiator budgets, while consistently maintaining thermally safe operation across diverse workloads. Our thermal-aware CIM design space exploration and radiator-in-the-loop co-design methodology opens an exciting avenue for developing scalable, energy-efficient AI accelerators for space-based data centers under stringent thermal constraints.

References↩︎