1 Educational contribution↩︎

FREESS addresses a recurring teaching difficulty in advanced computer architecture: the complexity of tracking the dynamic scheduling evolution of the hardware structures that implement a superscalar processor. The simulator makes this evolution explicit. Instead of hiding the internal state behind a performance summary, it presents renamed operands, ready-status changes, queue occupancy, structural conflicts, and in-order retirement cycle by cycle. The result is a didactic environment centered on how Tomasulo-style execution really unfolds in hardware [1], [2].

A key contribution is the choice of a compact, textual, and fully synchronized representation of the machine state. This view keeps the causal relation among instructions, resources, and stalls immediately visible. Students can therefore connect dependence chains, buffer pressure, issue bandwidth, and commit constraints without switching among disconnected windows or abstractions. This is especially useful in classroom discussion and in exam-oriented exercises, where the same trace can be mirrored on paper and reasoned about step by step.

2 Modeled machine and execution environment↩︎

FREESS models a compact superscalar processor around seven instructions: ADD, ADDI, BEQ, BNE, LW, MUL, and SW. The instruction set is intentionally minimal but sufficient to expose the main mechanisms of a superscalar CPU: fetch, renaming, out-of-order dispatch, execution, completion, commit, speculative branching, and memory access. Figure 1 summarizes the architectural structures used for this purpose.

The simulator is implemented in C, runs from the command line, and prints a complete cycle-by-cycle trace. The environment is lightweight enough to run easily in a standard teaching setup, yet configurable enough to compare multiple machine organizations. Users can modify superscalar issue width, the number and type of functional units, operation latencies, architectural buffer sizes, queue dimensions, and the number of loop iterations. These controls make it possible to study how a single kernel behaves under different hardware assumptions.

A particularly useful feature is the unified visibility of current state and recent execution history. For each cycle, FREESS shows renamed registers, instruction-window entries, reorder-buffer slots, queue contents, stage occupancy, and the dynamic progress of each instruction. Stall causes are reported explicitly, both in the main trace and in a dedicated log, so structural hazards, unavailable operands, limited issue bandwidth, branch effects, and commit bottlenecks can be discussed directly. Small programs are entered in a simplified machine-code form, which keeps the focus on instruction semantics and microarchitectural behavior rather than on assembler details.

3 Open source and classroom use↩︎

FREESS is openly released at https://github.com/robgiorgi/freess. This is more than a distribution detail: the code base is small enough to be inspected and adapted by instructors, while the execution model is simple enough for students to experiment with their own kernels and configurations. The open-source availability therefore extends the tool from a demonstrator to a reusable teaching platform [2].

The simulator has been used since 2010, that is, for about fifteen years, in the Advanced Computer Architecture course at the University of Siena. Across many course editions, it has supported lectures on superscalar execution, guided exercises on dynamic scheduling, and discussion of branch behavior. This long deployment is important because it shows that the interface and the modeled machine were refined against real teaching needs.

Compared with educational simulators such as SIMDE and SATSim, and with recent RISC-V-oriented teaching tools, FREESS emphasizes compact visibility of full-machine evolution over richer but more fragmented interaction [3]–[5]. That design choice makes it effective for understanding why instructions may complete out of order while still committing in order, and why limits in queues, or functional units translate into observable stalls and throughput changes.

Figure 2 illustrates this approach. In one screen, students can observe issued instructions, completed operations, queue and buffer state, and the textual explanation of the factors currently limiting progress.

4 Availability as a Web-Based Tool↩︎

FREESS is provided both as a standalone portable C program and as a web-based educational tool accessible at https://robgiorgi.github.io/freess/. This dual availability improves accessibility in teaching scenarios. The portable C implementation supports local execution, offline use, and direct inspection of the source code, whereas the web version enables immediate use from a browser without installation. Together, these two forms make FREESS both easy to adopt in classroom demonstrations and flexible enough for hands-on experimentation by students and instructors.

5 Conclusions↩︎

FREESS provides a configurable and cycle-accurate educational environment for visualizing Tomasulo-style superscalar execution in a RISC-V-inspired setting. Its main strength is not architectural breadth, but pedagogical clarity: the machine structures that govern dynamic scheduling remain visible, synchronized, and directly traceable throughout execution.

References↩︎