The rapid proliferation of artificial intelligence, connected devices, and high speed mobile networks is driving unprecedented computational demands that challenge traditional sensor architectures. This article explores the shift toward edge computing, where computation is performed directly at the data source, and highlights the key architectures and performance metrics that may define the next generation of intelligent sensor systems.

Advances in science have historically been driven by the development of instruments that extend human sensory capabilities. Over time, these tools have evolved into the sophisticated yet ubiquitous devices we now call sensors. Early sensors, such as thermometers, mercury barometers, and magnetic compasses, were standalone mechanical or chemical systems. They did not need external power or computation. With the rise of electronic computing, sensors became the perceptual front ends of digital systems. Today, sensors are no longer seen as passive recorders of physical signals. They can be part of computational systems or stand alone and respond intelligently to their environment[1]. This transformation is unfolding largely along architectural paths. The established approach uses conventional digital microarchitecture, integrating microcontroller units[2]–[6] (MCUs) or microprocessor units[7]; [8]; [9]; [10]; [11]; [12] directly within sensing hardware, but separated from the sensor unit. These systems follow traditional Von Neumann principles, keeping sensing, memory, and computation separate, and rely on synchronous, clock-driven operation, ultimately being limited by CMOS process constraints and interconnects. A more recent and disruptive approach integrates computation directly into the physical sensor unit (see Figure 1). In this in-sensor computing (ISC) paradigm, computation is performed either within the sensing element itself at the pixel level (in-pixel computing (IPC)) or in close physical proximity to the sensing array (near-sensor computing (NSC)). Emerging implementations of these architectures draw inspiration from biological systems, particularly the mammalian brain[13]–[21]. This paradigm is evolving along two complementary directions. The first emulates biological computation through spike-based encoding, where information is transmitted only upon changes in the input signal, broadly referred to as a neuromorphic architecture. The second focuses on structural integration, in which sensing and computation are physically co-located and tightly coupled through synaptic dynamics[22], broadly referred to as in-memory computing (IMC).

In the first of these biology inspired approaches, sensing elements can approximate the continuous differential equations governing neuronal behavior directly in the physics of the underlying circuits. In this neuromorphic architecture, each sensory pixel acts as an independent unit, similar to a biological neuron. It integrates the input signal and fires in response to temporal changes in the stimulus. The output is encoded as streams of spike trains, address event representations, or a combination of both. These representations are generally described as spike based encoding. A prominent example of a neuromorphic framework is event based neuromorphic vision sensors. Unlike traditional frame based vision sensors, which sample light intensity at fixed intervals, event-based neuromorphic sensors respond asynchronously to logarithmic changes in illumination[23]. This spike driven principle extends to other sensory modalities, including auditory, tactile, and olfactory[24]–[26]. In certain neuromorphic architectures, the physical structure of the sensory pixel becomes morphologically similar to neuronal motifs[27], [28]. The pixel embeds not only neuronal function but also structural features that resemble biological counterparts. The second approach enables computation directly within the sensor. In this architecture, the sensing elements can remain conventional. However, instead of simply streaming raw data off sensor, processing can take place locally. This localization can be achieved either through tight integration with a processing unit or by enabling computational capabilities within individual pixels. A prominent example of the first approach here are vision systems that stack an image processing digital tier with the sensing array. In this scheme, pixel data can be stored and processed in real time within the processing tier[29]. For spike-based sensor pixels, the processing tier itself can adopt a neuromorphic architecture, leveraging rich neuronal dynamics such as spiking neural networks. In the second approach, certain computational capabilities are embedded at the pixel level. This allows the sensor array to produce preprocessed outputs instead of raw signals. These outputs can then be further processed in a processing unit for more advanced operations[30], [31].

This growing diversity of approaches to embedding intelligence in sensors raises important questions about the future ecosystem and scaling trajectories. The strong asymmetric resource constraints across different sensing modalities and applications, however make it difficult to develop a unified framework. For example, automotive platforms can tolerate large resource budgets, such as chip area and thermal design power, but demand very low latency. In contrast, wearable biometric sensors operate under strict power and area limits but can tolerate higher latency. We develop a Power-Delay-Area (PDA) mapping framework to address this (see Figure 2a-b). At the heart of the framework is a semi-empirical scaling relationship \(P = k \cdot \frac{A}{L^{n}}\), where \(P\) denotes power, \(A\) denotes the functional/active area (hardware complexity), and \(L\) latency. This formulation encodes three key insights. First, the constant \(k\) defines the intrinsic energy floor of an architecture, determined by the physical distance of data movement, compute organization and memory hierarchy. Second, the ratio \(A/L\) reflects the commonly noted reality that increasing system complexity (large \(A\)) or demanding rapid response (small \(L\)) inherently increases power consumption. Third, the exponent \(n\) characterizes the scaling efficiency of the architecture. While \(k\) sets the magnitude of power consumption, \(n\) dictates the penalty of performance; it captures how communication overhead and synchronization costs grow as latency is reduced and follows super–linear, linear, or sub–linear trends.

In synchronous MPU architectures that utilize operating systems (OS) to enable multi-tasking, the scaling regime is typically super-linear (\(n > 1\)) due to the compounding costs of global coordination. To meet stringent timing constraints, interconnect topologies must adopt wider metal pitches, deeper pipelines, and aggressive buffering via repeaters and synchronization registers. These changes create a parasitic feedback loop: wider wires increase switching capacitance, while deeper pipelines introduce register overhead and branch-misprediction penalties. When latency is pushed further, the necessity of scaling supply voltage causes the power trajectory to further increase due to the quadratic relationship in the voltage-limited regimes. Simultaneously, the proportionality constant \(k\) is inflated by the fixed infrastructure overhead. The inclusion of repeater chains, global clock trees to synchronize deep pipelines, and the leakage from additional synchronization registers significantly raises the architecture’s energy floor. \(k\) is further inflated by data management overhead such as of coherence directories for cache management and the logic required for complex instruction-set decoding. Consequently, in these general-purpose regimes, the total power cost increases faster than the latency benefit, driven more by the systemic overhead of the physical cost of the communication fabric and data management.

MCU provides the first structural inflection point by enabling compute to be placed inside or immediately adjacent to the sensor, such as in system in package integration. This transition shifts the system toward a near–linear trajectory \((n \approx 1)\) because the dominant I/O energy and complexity associated with OS-level overhead, memory management, and pipelining are reduced, and clock frequency is typically fixed. However, while the slope parameter \(n\) improves, the baseline constant \(k\) remains comparatively elevated because signals must still traverse long horizontal metal interconnects across the two-dimensional plane of the die. These lateral on-chip communication require high-current off-chip drivers and retain parasitic capacitance. Three-dimensional stacking represents the next major step, leading to improved NSC, where sensing and computation are integrated within a single vertically organized structure. In this architecture, computational circuitry is placed directly beneath the pixel array and interconnected through dense vertical links such as through-silicon vias or hybrid bonds[29], [32]. This vertical organization fundamentally changes the geometry of data movement by replacing long planar communication paths with extremely short vertical connections, bringing processing physically closer to where data is generated. Vertical integration collapses the physical distance between sensing and computation from millimeter-scale planar routes to micrometer-scale vertical interconnects, and ultimately to sub-micron copper-to-copper bonds. Because interconnect capacitance scales approximately with length, this short-wire topology directly reduces parasitic capacitance and lowers the baseline energy required for each operation (\(k\downarrow\)). The scaling exponent \(n\) improves as 3D integration enables a transition from serialized planar communication to highly parallel data movement. As the pitch of vertical interconnects shrinks, their density increases quadratically, allowing many more signals to be transferred simultaneously between sensing and compute layers. This massive increase in parallel bandwidth reduces communication bottlenecks and drives the effective scaling behavior toward a more favorable, near-linear regime. Neuromorphic architectures represent the most energy-efficient operating regime, combining a sub-linear scaling exponent \((n < 1)\) with a small prefactor \(k\). As spike encoding is implemented directly within the sensory pixels, neuromorphic architectures naturally realize the IPC framework. The sub-linear behavior originates from abandoning the global clock in favor of temporally sparse, event-driven and in some cases logarithmically compressed computation[33]. Because only active sensory pixels consume dynamic power, the penalty for reducing latency is confined to the pathways that are actually used, while the large inactive regions contribute essentially no marginal cost. Similarly, the prefactor \(k\) is minimized through near-threshold or sub-threshold voltage operation and the use of low-leakage devices. In this regime, the interconnect component within \(k\) is further optimized through localized peer-to-peer signaling, which avoids the overhead associated with global bus structures. In a 3D configuration, where sensing and computation are vertically co-located, \(k\) approaches its minimal value.

In this phenomenological perspective, architectural efficiency is not a single scalar metric but rather a coupled description of where the power curve originates and how steeply it rises under increasing performance pressure, represented by the parameters \((k,n)\). Within this framework, we define a metric \(\psi\) that quantifies the physical efficiency with which an intelligent sensor converts sensed data into actionable computation. \(\psi\) is a product of the architectural quality (\(\zeta = \frac{1}{k \cdot n}\)), as the intrinsic efficiency of the micro-architecture, scaled by the compute density (\(\rho= \frac{T}{A}\)), where \(T\) denotes computational throughput, and scales directly with number of processing elements (\(N\)) and low latency. Current integration trends in sensing and emerging compute paradigms indicate a progressively increasing value of \(\psi\). From an integration perspective (see Figure 3a-b), as previously discussed, shorter interconnect lengths, result in lower energy per transfer and higher interconnect densities, which enable increased data transfer rates. From a computational perspective, shorter interconnect distances reduce latency. They also enable scaling to a large \(N\), particularly through emerging paradigms such as IMC architectures. Moreover, the higher achievable data rates can allow processors to be overclocked, enabling higher throughput. Using \(\psi\), the evolution of sensor generations can be projected as they become progressively optimized for architecture and compute. This progression is described in three distinct phases, each characterized by the dominant source of improvement. The initial phase is primarily driven by enhancements in \(\zeta\). The second phase is characterized by improvements in \(\rho\), enabled by scaling up the number of processing elements (\(N\)) and by architectural strategies such as weight stationarity through IMC, and close-memory access through 3D-integration. The final phase transitions to an event-driven regime, in which performance gains are again predominantly governed by advances in \(\zeta\). These improvements can be further casted onto roofline framework by defining the parameter \(\psi\) as a measure of how closely a system can approach peak throughput across a wide range of arithmetic intensities. Increasing \(\psi\) can enable compute near the peak-performance limit even for low algorithmic arithmetic intensity workloads, thereby making the sensor a favorable compute-bound hardware platform rather than a bandwidth-limited one (see Figure 3c).

Even further gains in sensor efficiency become possible when computation and memory are embedded directly within the sensory pixel. In this in-pixel-in-memory (IPC-M) framework regime, \(\psi\) approaches a theoretical asymptote, representing its fundamental upper bound, as architectural and interconnect overheads are minimized through the statefulness of the system. Within such architectures, \(k\) transitions from representing an interconnect penalty to capturing a direct physical state transformation, while \(n\) converges toward its most efficient event-driven limit. The sensory pixels are realized using emerging materials capable of programmable in-pixel computation during sensing[30], or through integration with memory elements that enable reconfigurable operation[34]. In both cases, the pixel output becomes a precomputed value rather than raw data[30]. For single-stage computational tasks, such as image recording or filtering, this approach approaches maximal efficiency. For more complex, multi-stage processing pipelines, it can serve as an effective front-end stage, for example as the initial layer of a convolutional neural network, that can be combined with the 3D NSC. This remains an active and evolving research area, with ongoing efforts aimed at incorporating temporal dynamics directly within the pixel, including short-term plasticity and related adaptive mechanisms[35]–[38].

In summary, we have outlined and categorized the evolving landscape of sensor technologies and the technological advances shaping their future. Crucially, sensors are improving not only in their ability to capture signals with greater fidelity, but also in their ability to process sensed data more efficiently. This dual progression (enhancing both sensing and computation) marks a broader transition from the era of transistor density, toward an era defined by intelligence density, where the value of a system will be increasingly determined by how effectively it can transform sensed information into actionable computation. This, in turn, will be governed by how efficiently data can be communicated, underscoring progress trends in interconnects, compute and system integration.

Methods↩︎

0.0.0.1 Area–Latency Scaling:

Latency can be considered in a normalized form as \(L/L_{\mathrm{ref}}\), where \(L_{\mathrm{ref}} = 1\,\mathrm{s}\) is chosen to fix the units of \(k\). On a log–log scale, the PDA analysis yields a first-order linear relationship, \(\log L = \frac{1}{n}\log A + \frac{1}{n}\log\!\left(\frac{k}{P}\right)\). The slope \(m = \tfrac{1}{n}\) captures area–latency sensitivity, while the intercept \(b = \tfrac{1}{n}\log\!\left(\tfrac{k}{P}\right)\) reflects the influence of architectural efficiency \(k\). Architectures with smaller \(n\) benefit more strongly from area scaling, whereas reductions in \(k\) shift the curve downward.

0.0.0.2 Intelligence Density Metric:

On the account of the used approach, we simplify the definition of intelligence to the capacity for high-efficiency information processing. While we discount the qualitative nature or breadth of the processing (reasoning, logic, etc.), this allows for a deterministic metric, \(\psi\), which measures the physical limits of hardware in converting sensed signals into actionable compute. The theoretical scaling of \(\psi\) follows the relationship \(\psi(g) = \left[ \frac{1}{k(g)\, n(g)} \right]\left[ \frac{N(g)}{A(g)\, L(g)} \right]\), where \(g\) denotes the technology generation. The theoretical frontier can be interpreted as the sum of the individual scaling contributions. Expressing the relationship in logarithmic form, and for a select generation yields \(\log \psi = \log N-\log\!\left(k\right) -\log\!\left(n\right) -\log A-\log L\). This expression shows that the scaling trajectory of \(\psi\) is determined by the additive contributions of improvements in architectural efficiency \((k,n)\) and compute density \((N/LA)\). Within a roofline-style analysis, \(\zeta\) should be interpreted primarily as a measure of the energy efficiency of data movement, rather than bandwidth itself. Bandwidth and \(\zeta\) become directly related only under the constraint of a fixed power budget. In this regime, higher energy efficiency in data movement enables proportionally higher achievable \(\text{bandwidth} = V \times \frac{\text{Power}}{\text{Energy per Byte}}\), where \(V\) represents the number of data lanes/vias. The peak performance, however, is a direct function of the compute density (\(\rho\)). The knee point is defined as the arithmetic intensity at which bandwidth equals peak performance, given by \(I_{\text{knee}} = \frac{\rho}{\zeta}\).

COI Statement↩︎

The author declare no competing interests.

Acknowledgments↩︎

The author would like to thank the MemVerse group (Dr. Abu Sebastian, Dr. Manuel Le Gallo, Mr. Loris Coccia, Ms. Jinane Bazzi) at IBM Research Zurich for their proofreading of the manuscript. The work is supported through European Research Council Starting Grant INFUSED (101222715).

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