1 Introduction↩︎

As digital control becomes increasingly popular in power converters, its advantages in cost, programmability, and integration over analog designs have made it the preferred choice. [1] In particular, it greatly simplifies the realization of sophisticated algorithms. Moreover, it enables over-the-air (OTA) firmware updates, allowing deployed products to gain new functionality without hardware modifications.

In common engineering practice, digital power converter design typically begins with power stage modeling using the classical state-space averaging (SSA) technique [2], [3]. An analog compensator is then designed in the continuous-time domain, discretized, and finally implemented in the digital controller. By averaging the piecewise linear state-spaces over one switching period, SSA eliminates the non-linearities. However, SSA neglects essential effects, such as computational delays, sampling, the presence of ripples, and sideband component coupling. [4] Consequently, SSA loses validity even if the perturbation frequency is far below the switching frequency. While SSA leverages well-established linear time-invariant (LTI) control theory for rapid design, it fails to provide an accurate prediction of the closed-loop stability, particularly when the crossover frequency approaches the sampling frequency, leading to a potential risk of instability.

To extend the model accuracy near or beyond the switching frequency, the sideband effect must be taken into account to form a multifrequency model[5]. As an extension to SSA, the generalized state-space averaging method (GSSA)[6]–[9] introduces Fourier series to account for higher-order harmonics in the time-domain waveforms. Based on the linear time-periodic (LTP) theory[10], the harmonic state-space (HSS)[11]–[13] and harmonic transfer function (HTF)[14], [15] methods have been proposed to model frequency coupling effects. HSS employs the harmonic balance principle[16] to represent an LTP system as an infinite-dimensional matrix equation set[5], while HTF captures both direct and cross-frequency interactions. While these multifrequency modeling methods greatly enhance accuracy, they tend to produce high-order models that are computationally intensive. Consequently, computer-based tools are required, and obtaining a simple closed-form solution is often not possible.

As a compromise between model accuracy and computational complexity, researchers have proposed simplified models that include only a limited number of sidebands. Two-frequency models proposed by [17] and [18] considered one sideband component other than the perturbed frequency \(f_p\). By considering a pair of sideband components and the switching frequency component, [19] fixes the low-frequency phase error in two-frequency models. An extended frequency model that incorporates all sideband components to enhance accuracy under large ripple conditions was proposed in [20]. However, the analytical form of the transfer function was not provided in [20].

The describing function (DF) method [21], [22] enables accurate derivation of closed-loop transfer functions and has been successfully applied to current-mode [23] and constant on-time (COT) [24] controlled Buck converters. It has also been extended to multiphase COT converters with phase overlapping [25], [26], and to passive-ripple architectures with exponentially decaying slopes [27]. To simplify the design process, equivalent circuit models based on Pade approximation have been proposed in [22]–[24]. Despite its impressive accuracy, the DF method provides limited physical insight, does not provide open-loop characterization, and involves cumbersome, topology-specific derivations.

Based on the sampled-data approach [28], a unified modeling method for various ripple-based control schemes is proposed in [29], [30]. By applying Shannon’s sampling theorem and infinite series summation, all sideband components are rigorously captured. Similar to the DF method, the sampled-data model remains accurate even beyond the switching frequency and does not rely on the small-ripple assumption. Additionally, it provides open-loop information and features a much simpler derivation process than DF-based models.

Although significant progress has been made in modeling analog-controlled converters, modeling efforts dedicated to digitally controlled converters remain comparatively limited. [30] extends the sampled-data approach to digitally controlled buck converters and derives an open-loop transfer function in the s-domain. Based on standard z-transform theory, [31] proposes a discrete-time model that accounts for the sampling and delay effects introduced by digital modulators, greatly simplifying digital compensator design.

The influence of modulation strategies on system dynamics has also been explored. Fig.1 presents the modulation strategies. For example, [32] studies asymmetric carrier modulations and analyzes how leading-edge modulation (LEM) and trailing-edge modulation (TEM) affect loop stability and transient response in analog modulators, while [33] further investigates symmetric carrier modulation. [34] compares LEM and TEM in digital pulse-width modulators (DPWM) and proposes a second-order global equivalent circuit to facilitate controller design. [35] demonstrates that adopting LEM in a digitally controlled boost converter can eliminate the right-half-plane zero to enhance transient performance.

In addition, [36] and [37] show that different injection points and perturbation injection methods yield different loop gain measurements in digitally controlled converters. [37] further establishes the relationship between the responses obtained under different injection methods. Furthermore, [38] considers the case where the sampling rate is lower than the switching frequency and proposes a corresponding design methodology.

However, the impact of DPWM-ADC synchronization in digitally controlled converters has not been investigated in previous works. In practical implementations, the ADC sampling instant in digital buck converters is often dynamically aligned with the duty cycle, such that sampling occurs at the center of the on-time or off-time interval. This ensures the sampled inductor current approximates its average value under steady-state. However, such synchronization affects small-signal characteristics. The duty cycle perturbation affects the ADC samples. Despite its widespread use in engineering practice, to the authors’ best knowledge, this effect has not yet been accounted for in any existing small-signal model.

The remainder of this paper is organized as follows. Section II presents the small-signal sampled-data modeling under asymmetrical carrier modulation with explicit consideration of DPWM-ADC synchronization. A closed-form expression of the digital loop gain is derived using the modified z-transform, and it is shown that the analog loop gain can be obtained from the digital loop gain, thereby avoiding complicated infinite-series evaluations. Although the derivation begins with trailing-edge modulation (TEM), the conclusions are also extended to leading-edge modulation (LEM). Section III develops the small-signal model for the case of a symmetrical carrier. Section IV compares the proposed model with the simulation results and existing models, demonstrating its superior accuracy. Section V provides experimental validation, confirming that the proposed model exhibits good agreements in all cases. Finally, Section VI concludes the paper.

Throughout this paper, lowercase variables with a time argument (e.g. \(i_L(t)\)), denote time-domain signals that include both the periodic steady-state component (denoted by uppercase variables with a time argument, e.g. \(I_L(t)\)) and the small-signal perturbation (denoted by a hat, e.g. \(\hat{i}_L(t)\)). The DC value of a signal is indicated by an overline, e.g. \(\overline{I_L}\).

2 Small-Signal Modeling of Digital Buck Converters with Asymmetrical Carriers↩︎

Fig. 2 illustrates a digitally controlled synchronous Buck converter employing current-mode control and operating in forced continuous conduction mode (FCCM). The digital counter generates an up-counting sawtooth carrier (\(CNTR\)) with an amplitude of \(CNTR_{MAX}\). When \(CNTR\) reaches zero, the counter updates the shadow register. The shadow register serves to suppress spurious PWM pulses during abrupt changes in the duty-cycle command. The DPWM output will be high if the shadow register output is higher than \(CNTR\) and will be low elsewhere. This configuration implements a TEM DPWM, in which the PWM rising edge is fixed at the beginning of each cycle, while the falling edge varies and moves according to the duty-cycle command.

To simplify the analysis, the steady-state ADC sampling instant (\(kT_S\)) defines the beginning of each cycle. The block diagram and timing are presented in Fig.2 and Fig.3, where \(H_i\) is the current sensor gain and \(T_s\) is the switching period. In practice, \(H_i\) also includes the ADC gain. The scaled inductor current is denoted as \(i_s\). The duty-cycle to the inductor current transfer function and the digital PI compensator transfer function[30] are:

\[G_{id}(s) = V_{IN}\bigg[sL_f+R_L+(\frac{1}{sC_f}+R_C) \parallel R_{LD}\bigg]^{-1} \label{eq:gid}\tag{1}\]

\[G_C(z) = K_P+\frac{K_iT_s}{1-z^{-1}} \label{eq:digital95pi}\tag{2}\]

The ADC and shadow register are modeled as sample-and-hold blocks. Under the small-signal assumption, the DPWM behaves as an ideal sampler, allowing the duty-cycle perturbation \(\hat{d}\) to be treated as an impulse train [29]. When a sampling-hold-sampling sequence operates at the same sampling frequency, it can be equivalently represented by a single sampler followed by a delay equal to the time difference between the two sampling instants (proof provided in Appendix I). By applying this lemma twice, the 3 samplers and 2 ZOH blocks in Fig.2 can be simplified to a single sampler followed by a delay \(T_D\), without any ZOH. Under the small-signal assumption, \(T_D\) is defined as the steady-state time between the ADC sampling instant and the moment when the new calculated duty-cycle command takes effect.

Since DPWM-ADC synchronization guarantees that sampling always occurs at the PWM on-interval center, as shown in Fig.4, in each cycle, the ADC sampling instant \(t_{smp}\) is related to the on-time perturbation \(\hat{t}_{on}\) of the previous cycle:

\[t_{smp\_k} = kT_S+0.5\hat{t}_{on}[k-1] \label{eq:t95smp95k}\tag{3}\]

Under the small-signal assumption, the k-th sampled inductor current \(i_L(t_{smp\_k})\) can be approximated its 1st-order Taylor expansion as:

\[i_s(t_{smp\_k}) \approx i_s(kT_S)+\frac{di_s(t)}{dt}\bigg|_{t=kT_S} \times \frac{\hat{t}_{on}[k-1]}{2} \label{eq:is95smp95k}\tag{4}\] where \(i_s(kT_S)\) is the scaled inductor current sampled at fixed instants \(kT_S\), \(I_s(kT_S)\) is the steady-state sampled inductor current, which equals the average inductor current \(\overline{I_L}\): \[i_s(kT_S) = i_s[k] = I_s(kT_S) + \hat{i}_s[k] = \overline{I_L}H_i+\hat{i}_s[k] \label{eq:is95kts}\tag{5}\] Extracting perturbation terms from 4 and 5 yields: \[\hat{i}_{smp}[k] = \hat{i}_s[k] + \frac{di_s(t)}{dt}\bigg|_{t=kT_S} \times \frac{\hat{t}_{on}[k-1]}{2} \label{eq:i95smp95hat}\tag{6}\]

Therefore, with 6 and Lemma 1, Fig.2 can be simplified to Fig.5. \(G_{CM}(s)\) represents the analog feedback-to-modulator output transfer function and accounts for the side-band effects due to sampling, the "CM" subscript stands for controller and modulator. \(G_{Plant}(z)\) denotes the plant seen by the digital PI compensator \(G_C(z)\). The transfer function of the pure discrete part in Fig. 5, from \(\hat{i}_s[k]\) to \(\hat{t}_{on}[k]\), can be derived as:

\[G_D(z) = \frac{-G_C(z)\frac{T_S}{CNTR_{MAX}}}{1-[-G_C(z)\frac{T_S}{CNTR_{MAX}}]\times H_{sync}(z)}\] where the feedthrough due to DPWM-ADC alignment is: \[H_{sync}(z) = \frac{z^{-1}}{2}\frac{di_L(t)}{dt}\bigg|_{t=kT_S} \times H_i\]

According to the sampling theorem, the impulse train \(\hat{i}_s[k]\)’s s-domain representation \(\hat{i}_s^*(s)\) is: \[\hat{i}_s^*(s) = \hat{i}_s^*(s+jn\omega_S) = \frac{1}{T_s} \sum_{n=-\infty}^{\infty} \hat{i}_s\!\left(s + j n \omega_s\right) \label{eq:is95sampling}\tag{7}\] isolating the \(n=0\) case of the infinite summation gives: \[\hat{i}_s^*(s) = \frac{1}{T_s}\hat{i}_s(s) + \frac{1}{T_s}\sum_{\substack{n=-\infty \\ n \neq 0}}^{\infty} \hat{i}_s\!\left(s + j n \omega_s\right) \label{eq:is95sampling95expanded}\tag{8}\] The second term of 8 models sideband couplings. From Fig.5, \(\hat{i}_s(s)\) can be expressed as: \[\hat{i}_s(s) = \hat{t}_{on}^*(s)e^{-sT_D}G_{id}(s)H_i \label{eq:i95s95continuous}\tag{9}\] Since \(\hat{t}_{on}[k]\) is also an impulse train, its s-domain representations are: \[\hat{t}_{on}^*(s) = \hat{t}_{on}^*(s+jn\omega_S) = G_D(e^{sT_S})\hat{i}_s^*(s) \label{eq:d95hat95discrete}\tag{10}\] Expanding the infinite summation term in 8 with 9 and then replacing \(\hat{t}_{on}^*(s+jn\omega_S)\) with \(\hat{t}_{on}^*(s)\) according to 10 gives: \[\begin{align} \hat{i}_s^*(s) = \frac{1}{T_s}&\bigg[\hat{i}_s(s)+\hat{t}_{on}^*(s)\times\\ &\sum_{\substack{n=-\infty \\ n \neq 0}}^{\infty}e^{-(s+jn\omega_S)T_D}G_{id}(s+jn\omega_S)H_i\bigg] \end{align} \label{eq:is95star95expanded}\tag{11}\] Substituting 11 into 10 to eliminate \(\hat{i}_s^*(s)\), then isolating \(\hat{t}_{on}^*(s)\) and \(i_s(s)\) gives: \[\begin{align} &\frac{\hat{t}_{on}^*(s)}{\hat{i}_s(s)} = \frac{\frac{G_D(z)}{T_S}}{1 - \frac{G_D(z)}{T_S} \displaystyle\sum_{\substack{n=-\infty \\ n \neq 0}}^{\infty} e^{-(s+jn\omega_S)T_D}G_{id}(s+jn\omega_S)H_i} \\&\quad\quad\quad\text{where: } \quad z=\exp(sT_S) \end{align} \label{eq:is95to95d}\tag{12}\]

Hence, \(G_{CM}(s)\) can be derived from 12 as: \[G_{CM}(s) \triangleq -\frac{\hat{d}(s)}{\hat{i}_s(s)} = -e^{-sT_D}\frac{\hat{t}_{on}^*(s)}{\hat{i}_s(s)}\]

The analog loop gain \(T_i\) can be expressed as:

\[T_i(s) = G_{CM}(s)G_{id}(s)H_i\]

From Fig. 5, the plant transfer function seen by the digital compensator can be easily found as:

\[G_{Plant}(z) = \frac{T_S}{CNTR_{MAX}} \bigg[H_{sync}(z)+G_{MZ}(z) \bigg] \label{eq:G95Plant}\tag{13}\] where: \[G_{MZ}(z)=\frac{1}{T_S}\displaystyle\sum_{\substack{n=-\infty}}^{\infty} \big[e^{-sT_D}G_{id}(s)H_i\big]_{s->s+jn\omega_S} \label{eq:G95MZ}\tag{14}\]

The digital loop gain \(T_{pul}\) is then: \[T_{pul}(z) = G_{Plant}(z) G_C(z) \label{eq:T95pul}\tag{15}\]

The loop gain measurement reads differently as the injection point changes [36], [37]. The relationship between \(T_i\) and \(T_{pul}\) is found to be:

\[T_i(s) = \frac{T_0(s)}{1+T_{pul}(\exp(sT_S))-T_0(s)} \label{eq:ruan}\tag{16}\] where: \[T_0(s) = G_c(e^{sT_S})\frac{1}{CNTR_{MAX}}e^{-sT_D}G_{id}(s)H_i\]

16 agrees with the conclusion of [37] and provides a method to evaluate the analog loop gain from the digital loop gain. Furthermore, 14 resembles the modified Z-transform[39] of \(G_{id}H_i\) with a sampling delay of \(T_D\). One can perform partial fraction on \(G_{id}H_i\) and then utilize the following modified Z-transform identity to evaluate 14 :

\[\mathcal{Z}_m\!\left\{\sum_{r=1}^{\mathrm{PoleCount}}\frac{n_r}{s+d_r},\,T_p\right\} =\sum_{r=1}^{\mathrm{PoleCount}} \frac{n_r\,e^{d_r T_p}}{z\,e^{d_r T_S}-1}. \label{eq:Zm}\tag{17}\] where the delay \(T_p\) must satisfy \(T_p\in (0,\,T_S)\), i.e., strictly within one sampling period. If the desired sampling delay \(T_D\) is not in this range, it can be decomposed as: \[T_D = kT_S + T_p, \quad k \in \mathbb{Z}, \; T_p \in (0,\,T_S).\] In this case, the modified \(z\)-transform of a delay \(T_D\) can be obtained by multiplying \(z^{-k}\) with the modified \(z\)-transform of a delay \(T_p\): \[G_{MZ}(z)= \mathcal{Z}_m\{G_{id}H_i,\,T_D\}=z^{-k}\mathcal{Z}_m\{G_{id},\,T_p\}H_i. \label{eq:G95MZ95Calc}\tag{18}\] where in the case of TEM, \(k=1\) and \(T_p=0.5DT_S\), as shown in Fig.2 and Fig.3.

The above analysis for TEM can be extended to LEM. Table 1 summarizes the effective sampling delay \(T_D\) under different modulation modes and sampling strategies.

By applying 18 to 13 , the plant transfer function seen by the digital compensator can be obtained for both TEM and LEM cases, which provides the basis for loop compensation design, e.g., using the pole-placement method.

3 Small-Signal Modeling of Digital Buck Converters with Symmetrical Carriers↩︎

The above analysis for asymmetrical carriers can be extended to the case where the carrier is a symmetric triangular waveform. Fig.6 illustrates the key waveforms of a digital buck converter with a triangular carrier. The ADC samples when \(CNTR\) reaches 0, which corresponds to the center of the PWM on-interval. Afterwards, the new duty cycle command is loaded into the shadow register when \(CNTR\) reaches \(CNTR_{MAX}\). Compared to the asymmetrical case, two important differences arise. First, in the symmetrical case, the ADC sampling instant is always fixed with respect to the carrier and does not vary with any perturbation. Consequently, there will be no \(H_{\text{sync}}(z)\). Second, each impulse \(\hat{t}_{on}[k]\) now maps to two impulses in \(\hat{d}\) that have different delays (\(T_{D1}\) and \(T_{D2}\)), which is similar to the sampled-data COT model in [30].

In this case, the plant transfer function in the \(z\)-domain seen by the digital compensator is given by: \[\begin{align} G_{\text{Plant,SYM}}(z) = \frac{T_s}{2\,\text{CNTR}_{\max}} \bigg(&\mathcal{Z}_m \{G_{id}, T_{D1}\} + \\ &\mathcal{Z}_m \{G_{id}, T_{D2}\} \bigg) H_i \end{align} \label{eq:G95plant95sym}\tag{19}\]

where \(T_{D1}\) and \(T_{D2}\) are given in Table 2. This table also accounts for the alternative configuration where sampling occurs at the off-interval center, i.e., when \(CNTR = \text{CNTR}_{\max}\) and the shadow register is updated at \(CNTR=0\).

19 provides the plant transfer function for digital compensator design. The open-loop transfer function in the digital domain can then be computed from 15 , while the corresponding analog-domain loop gain can still be obtained directly using 16 . In this case, \(T_0(s)\) is modified as: \[T_{0,\text{SYM}}(s) = \frac{G_c(e^{sT_s})}{\text{2CNTR}_{\max}} (e^{-sT_{D1}}+e^{-sT_{D2}})G_{id}(s)H_i\]

4 Comparison Between Existing Small-Signal Models and the Proposed Analytical Model↩︎

For a fair comparison, all models are evaluated under the same set of circuit and control parameters, summarized in Table 3.

Fig. 7 compares the analog loop gain predicted by the proposed model, Yan’s model [30], and SIMPLIS simulation. The results were obtained under TEM modulation with turn-off-centered sampling. Since the proposed model explicitly incorporates the DPWM-ADC synchronization effect through the \(H_{\text{sync}}(z)\) term, its prediction shows excellent agreement with the simulation results. In contrast, Yan’s model [30] deviates by more than 45 dB lower, translating to significant inaccuracies in the predicted closed-loop gain(\(T_c(s)=T_i(s)/(1+T_i(s))\) [29]), as depicted in Fig. 8. This observation further confirms that, in a digitally controlled power converter, without proper synchronization between the ADC and the DPWM, the steady-state error cannot be fully eliminated even if the digital compensator contains an integral term.

Fig.9 presents the plant transfer function as perceived by the digital compensator, predicted by the proposed model, Dragan’s purely discrete-time model [31], and SIMPLIS simulations. It is observed that Dragan’s model, which neglects DPWM-ADC synchronization, consistently deviates from the simulation results. In contrast, the proposed model achieves an excellent match across the entire frequency range, validating its superior accuracy.

Fig. 10 illustrates the analog and digital loop gains using different perturbation methods. As reported in [36], [37], the two measurements exhibit close agreement in the mid-frequency range (approximately 100 Hz to half the switching frequency), but significant discrepancies appear at both low and high frequencies. At low frequencies, the digital loop gain behaves as an ideal integrator, theoretically yielding an infinite DC gain, whereas the analog loop gain settles to a finite value. This property can be rigorously verified by evaluating the limits of 16 and 15 as \(s \to 0\).

To further verify the effectiveness of the proposed model, Fig. 11 compares its predictions against SIMPLIS simulations under symmetrical modulation, where the ADC sampling is performed at the turn-off center.

5 Experimental Verification↩︎

To further validate the proposed model, a synchronous buck converter prototype was built as shown in Fig. 12. The controller is implemented on a floating-point DSP (TMS320F28379) running at 200 MHz. Both the switching frequency and ADC sampling rate are set to 100 kHz. A high-resolution PWM is employed such that the PWM resolution far exceeds the 12-bit ADC resolution, thus avoiding limit cycles caused by duty-cycle quantization. Because the resolutions of DPWM and ADC are sufficiently high, quantization effects are negligible in the control operation.

To capture parasitics including the ESR and DCR, \(G_{id}H_i\) is characterized by Bode 100 as:

\[G_{id}(s)\times H_i = \frac{3091003s+5165486753}{s^2+12168.2939s+648181436} \times 0.085 \label{ehlajogd}\tag{20}\]

The digital converter setup operates under TEM modulation with turn-on centered sampling, with controller gains set as \(K_p=0.2\) and \(K_i=0.2\). Fig. 13 shows the measured analog loop gain. The analog loop gain is obtained via Bode 100, using an injection transformer to insert perturbations as a voltage source between the ADC input and the low-side current-sensing resistor. Two input channels of the Bode 100 measure the voltages at both ends of the injection transformer relative to ground.

Fig. 14 presents the comparison of the digital loop gain predicted by the proposed model against measurements obtained via two distinct injection methods. In the first method, akin to that in [36], the DSP samples the perturbation signal from the Bode 100 analyzer, combines it in software with the sampled inductor current, and then outputs both the pre- and post-injection current samples via DACs back to the Bode 100. The second method implements a Software-based Frequency Response Analyzer (SFRA) directly on the DSP: the SFRA injects discrete sinusoidal perturbations in software at selected frequencies and applies a Discrete-Time Fourier Transform (DTFT) to extract the magnitude and phase response at each frequency. This procedure is repeated sequentially over the frequency range to construct the bode plot. Fig. 14 demonstrates that both measurement methods yield equivalent results and closely agree with the model predictions. The discrepancy observed around 4 kHz is primarily attributed to core losses in the inductor during operation, which were not accounted for during the \(G_{id}\) characterization.

The SFRA method enables digital-loop measurement without the need for additional hardware, and when combined with the highly accurate discrete-time model proposed in this work, it provides an effective framework for digital compensator design under real operating conditions.

References↩︎