Beyond Tokens: Enhancing RTL Quality Estimation via Structural
Graph Learning
August 26, 2025
Abstract
Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key metrics like area and delay without the need for time-consuming logic synthesis. While recent approaches have leveraged large language models (LLMs) to derive embeddings from RTL code and achieved promising results, they overlook the structural semantics essential for accurate quality estimation. In contrast, the control data flow graph (CDFG) view exposes the design’s structural characteristics more explicitly, offering richer cues for representation learning. In this work, we introduce a novel structure-aware graph self-supervised learning framework, StructRTL, for improved RTL design quality estimation. By learning structure-informed representations from CDFGs, our method significantly outperforms prior art on various quality estimation tasks. To further boost performance, we incorporate a knowledge distillation strategy that transfers low-level insights from post-mapping netlists into the CDFG predictor. Experiments show that our approach establishes new state-of-the-art results, demonstrating the effectiveness of combining structural learning with cross-stage supervision.
1 Introduction↩︎
As AI models continue to grow in size and computational demands, their success depends not only on algorithmic advances but also on the performance of the underlying hardware. Notably, it has been estimated that more than half of the performance gains in AI systems over the past decade can be attributed to improvements in hardware alone [1], [2]. This highlights the critical role of hardware innovation in driving and sustaining progress in AI. At the same time, the growing demand for specialized and high-performance hardware places greater pressure on the efficiency of the hardware design process itself. Consequently, there is a pressing need for new methodologies that can accelerate design cycles and improve design quality and performance.
Modern hardware design is a complex, multi-stage process that begins with high-level specifications in natural language, which are manually translated into hardware description languages (HDLs) such as Verilog or VHDL, before synthesizing into circuit elements. At the heart of this process lies the register transfer level (RTL), a critical abstraction that bridges architectural intent and low-level circuit implementation, enabling designers to model intricate digital systems in a way that is both expressive and amenable to synthesis into gate-level representations. Typically, RTL design is refined iteratively, with engineers assessing the quality of the synthesized netlist using key metrics such as area and delay. However, this feedback loop is inherently slow and computationally expensive, as each iteration requires invoking a full logic synthesis toolchain. To reduce design turnaround time and improve productivity, there is an increasing demand for fast and reliable methods that can estimate design quality directly from RTL, enabling early feedback without sacrificing accuracy.
To address the aforementioned issue, prior research has explored machine learning-based approaches that represent hardware code as graphs, e.g., abstract syntax trees (ASTs) and control data flow graphs (CDFGs), and use hand-crafted features derived from these graphs for quality estimation [3]–[5]. While these methods have shown encouraging results, their reliance on manually designed features significantly limits their expressiveness and ability to capture the rich structural semantics in RTL designs. As a result, these shallow representations often fail to capture the complex patterns that affect downstream performance, constraining their effectiveness for accurate quality estimation. Recently, with the rise of large language models (LLMs) [6]–[8], some approaches have attempted to derive embeddings from RTL code using LLMs specifically trained for Verilog generation [9]–[11], achieving state-of-the-art performance in quality estimation tasks [12]. However, a fundamental gap exists between the objectives of code generation and quality estimation, which may limit the transferability of representations learned from generation-focused pretraining. Besides, compared to CDFG, the token-based view encodes the structural semantics of RTL designs implicitly, providing fewer cues for learning, which may hinder the final performance.
In this work, we introduce StructRTL, a novel structure-aware graph self-supervised learning framework designed to improve RTL design quality estimation. Instead of using token-based view, StructRTL operates on the CDFG view, which more explicitly captures the structural semantics of RTL designs. Besides, rather than relying on shallow, hand-crafted features, our method employs two self-supervised pretraining tasks, i.e., structure-aware masked node modeling and edge prediction, to learn rich structure-informed representations from CDFGs. These pretraining objectives enable the model to capture complex dependencies and design patterns, leading to significant performance improvements over existing approaches on various quality estimation tasks. Furthermore, inspired by VeriDistill [12], we incorporate a knowledge distillation strategy that transfers low-level insights from post-mapping netlists into the CDFG predictor, further enhancing the model’s predictive capabilities. Experimental results demonstrate that StructRTL achieves new state-of-the-art performance, highlighting the effectiveness of combining structural representation learning with cross-stage supervision.
2 Related Work↩︎
2.1 RTL Design Quality Estimation↩︎
Early efforts to estimate RTL design quality have primarily relied on features extracted from graph-based representations of RTL code. For instance, one study explores delay prediction by converting RTL designs to data flow graphs (DFGs) and extracting internal cell connectivity statistics as features to predict post-synthesis critical path delay [13]. However, this approach has only been applied to simple combinational circuits such as adders and is trained on synthetic design variants generated by an RTL generator, limiting its practical applicability. Another work represents RTL code as AST and extracts hand-crafted features like total input and output bits and average wire width [4]. These features are then used to train traditional machine learning models like XGBoost [14] for quality estimation. Similarly, MasterRTL [5] converts RTL code to a new bit-level design representation called the simple operator graph (SOG) and extracts features from it for the same purpose. While these approaches have shown some promise, they share two key limitations. First, their reliance on hand-crafted features limits the expressiveness of the representation and fails to capture the rich structural semantics of RTL designs. Second, their training and evaluations are based on small datasets, typically fewer than 100 designs in total, raising concerns about the models’ generalization capabilities. Moreover, the construction of SOG requires invoking logic synthesis steps, placing it closer to the gate-level netlist stage rather than purely RTL. As such, it falls outside the scope of our work.
Recently, the rise of LLMs [6]–[8] has sparked growing interest in fine-tuning these models for Verilog code generation [9]–[11], [15], [16]. Based on this trend, VeriDistill [12] has proposed using LLMs specifically trained for Verilog generation to extract embeddings from RTL code, achieving state-of-the-art performance on RTL quality estimation tasks using a large dataset of over 10,000 designs. However, there remains a fundamental mismatch between the goals of code generation and quality estimation, which may limit the transferability of representations learned from generation-focused pretraining. Moreover, unlike CDFG, the token-based view encodes the structural semantics of RTL designs implicitly, offering fewer cues for learning. This lack of explicit structural information can make it more difficult for models to capture the patterns critical for accurate quality prediction.
2.2 Graph Self-Supervised Learning↩︎
Graph self-supervised learning, which learns generalizable representations from unlabeled graph data, has emerged as a popular and empirically successful learning paradigm for graph neural networks (GNNs) [17]. Broadly, these methods fall into two categories: contrastive and generative approaches. Contrastive methods aim to learn representations that are invariant to different augmented views of a graph [18]–[20], while generative methods create supervision signals by masking parts of the graph, such as node attributes or edges, and train the model to reconstruct the missing components [21], [22]. In this work, we adopt generative approaches to learn structure-informed representations for RTL design quality estimation.
Inspired by the success of BERT [23] in natural language processing (NLP), GraphMAE [21] demonstrates that masking a portion of node features and reconstructing them from their surrounding context can yield high-quality representations, achieving state-of-the-art performance on a variety of tasks. Complementarily, MaskGAE [22] focuses on the structural aspect by masking a subset of edges or even paths and training the model to recover the graph connectivity, thereby learning rich topological features. These approaches compel the model to decipher the underlying relational patterns within the graph, thereby generating robust and informative embeddings. However, directly applying these techniques to CDFGs of RTL designs poses challenges. Unlike general-purpose graphs, CDFGs are tightly coupled with computational semantics, where masking nodes or edges, such as an arithmetic operator, can introduce ambiguity. For instance, if a plus operator is masked, multiple replacements (e.g. minus, multiply), could all appear valid, undermining the learning signal. To address this, we design two tailored pretraining objectives: structure-aware masked node modeling and edge prediction. These adaptations allow us to preserve the computational integrity of CDFGs while still leveraging the benefits of generative self-supervision. Details of these techniques are presented in the following section.
3 Methodology↩︎
In this section, we present the details of our proposed framework, StructRTL. It incorporates two tailored pretraining tasks, structure-aware masked node modeling and edge prediction, to learn structure-informed representations that are essential for downstream RTL design quality estimation. To further enhance performance, we apply knowledge distillation, which transfers low-level insights from post-mapping (PM) netlists into the CDFG predictor, refining the model’s ability to estimate quality metrics accurately.
3.1 CDFG Construction↩︎
RTL is a design abstraction level used in digital circuit design that models the flow of data between registers and the operations performed on that data. It encompasses both combinational logic (e.g., arithmetic operations and control branches) and sequential logic (e.g., registers that store state across clock cycles). A common representation of RTL designs is CDFG, where nodes represent operations or storage elements, and directed edges indicate data or control dependencies between them. In sequential circuits, registers hold values between clock cycles, so their incoming edges represent inter-cycle data flow, making CDFGs cyclic graphs.
To construct a CDFG from RTL source code, we first use Yosys [24] to compile the design into RTL intermediate language (RTLIL), a simplified form that preserves functionality while reducing the design to basic assignment and register-transfer operations. This intermediate form makes CDFG extraction more straightforward. We then apply the Stagira Verilog parser [25] to generate an AST from the RTLIL. Finally, we traverse the AST to extract the CDFG. An example RTL design and its corresponding CDFG are shown in Figure 2. For more details on the CDFG, please refer to the Appendix.
3.2 Model Architecture↩︎
As illustrated in Figure 1, StructRTL integrates a GNN with a Transformer encoder [26]. Given a CDFG \(\mathbf{G}=(\mathbf{V},\mathbf{E})\), where \(\mathbf{V}\) denotes the set of nodes and \(\mathbf{E}\) represents the edges, we first initialize the node embeddings \(\{\mathbf{h}_{i}^{0}\}\) as the concatenation of the one-hot encoding of the node type and the node width: \[\mathbf{h}_{i}^{0} = \operatorname{concat}\left( \operatorname{one-hot}(\operatorname{type}(v_{i})), \operatorname{width}(v_{i}) \right)\] Next, message passing is performed on \(\mathbf{G}\) using a graph isomorphism network (GIN) [27] to process the node embeddings and obtain context-aware embeddings \(\{\mathbf{h}_{i}^{g}\}\). These updated embeddings are then fed into the Transformer encoder. To preserve the graph’s structural information, we combine \(\{\mathbf{h}_{i}^{g}\}\) with global positional embeddings \(\{\mathbf{p}_{i}\}\) [28]. This step is vital because when the node embeddings are flattened into a sequence for the Transformer, the graph’s connectivity information is lost. Without the global positional embeddings, the model would struggle to distinguish between similar nodes located in different parts of the graph, leading to training collapse.
To compute the global positional embeddings \(\{\mathbf{p}_{i}\}\), we first calculate the symmetric normalized Laplacian matrix for the directed graph [29]: \[L = I - D_{\text{in}}^{-1/2}AD_{\text{out}}^{-1/2}\] where \(A\) is the adjacency matrix, and \(D_{\text{in}}\) and \(D_{\text{out}}\) are the in-degree and out-degree matrices, respectively. We then compute the eigenvalues and corresponding eigenvectors of \(L\) by solving the equation: \[L\mathbf{x} = \lambda\mathbf{x}\] where \(\{\lambda_{i}\}\) are the eigenvalues and \(\{\mathbf{x}_{i}\}\) are corresponding normalized eigenvectors. To construct the global positional embeddings, we select the \(k\) eigenvectors corresponding to the smallest \(k\) eigenvalues, where \(k=16\) in this work. If the number of nodes is smaller than \(16\), we pad the embeddings with \(\mathbf{0}\). We then project \(\{\mathbf{p}_{i}\}\) using a linear projection layer to ensure it has the same dimensionality as \(\{\mathbf{h}_{i}^{g}\}\). Additionally, since eigenvectors \(\{\mathbf{x}_{i}\}\) are inherently sign-insensitive (i.e., both \(\mathbf{x}_{i}\) and \(-\mathbf{x}_{i}\) are valid eigenvectors for \(\lambda_{i}\)), we randomly flip the signs of the eigenvectors during training. This technique helps reduce the model’s sensitivity to the sign of the eigenvectors and improves its generalization ability. Finally, the combined embeddings are passed into the Transformer encoder, where they are transformed into final embeddings \(\{\mathbf{h}_{i}^{t}\}\) ready for downstream quality estimation via structure-aware masked node modeling and edge prediction.
3.3 Pretraining Tasks↩︎
In this work, we adopt two self-supervised pretraining tasks, structure-aware masked node modeling and edge prediction, to obtain structure-informed representations for RTL design quality estimation. Unlike prior methods that directly masks raw node features or edges in the original graph [21], [22], we apply masking at the level of post-GNN context-aware embeddings. This design choice is particularly important for computational graphs like CDFGs, where each node carries strict functional semantics. Masking raw nodes or edges in such graphs can introduce ambiguity, as multiple valid replacements exist. By instead masking the post-GNN embeddings, which already encode surrounding semantics, the model can utilize rich context information from unmasked regions to reconstruct the masked content. This preserves the structural and computational integrity of the original graph, enabling more faithful reconstruction.
Structure-Aware Masked Node Modeling. In this task, we randomly mask \(20\%\) of the post-GNN node embeddings by replacing them with a special learnable [MASK] embedding and use the
Transformer encoder to recover the masked nodes by predicting their corresponding types, which is formulated as a 32-class classification problem. A complete list of node types is provided in the Appendix. One key challenge in this task is the severe class
imbalance. For example, operator nodes are significantly underrepresented compared to storage elements such as wires and registers. To mitigate this, we adopt two strategies. First, we apply stratified masking, which ensures that at least \(m\) nodes from each class are included in the masked set during each training iteration. This helps the model to learn meaningful representations even for infrequent node types. The full procedure is described in Algorithm 3. Second, instead of using the classic cross entropy loss, we adopt the class-balanced focal loss [30],
which adjusts the loss based on the effective number of samples for each class, and puts more focus on hard-to-classify examples. The details of the class-balanced focal loss are presented in Algorithm 4. The loss function
for this task is denoted as \(\mathcal{L}_{mnm}=\mathcal{L}_{cb\_focal}\).
Edge Prediction. When the post-GNN embeddings are input into the Transformer encoder, the graph’s connectivity is lost, which can be viewed as if all edges are masked. For each training iteration, we randomly select \(20\%\) of the actual edges as positive samples and an equal number of non-existing edges as negative samples, and formulate the edge prediction task as a binary classification problem. Specifically, we concatenate the final embeddings of the source and target nodes and use a 3-layer multi-layer perceptron (MLP) to predict whether an edge exists between them. We employ cross entropy loss for this task, and denote the loss as \(\mathcal{L}_{ep}\).
The total loss for pretraining is: \[\mathcal{L}_{pre}=\alpha\mathcal{L}_{mnm}+\left(1-\alpha\right)\mathcal{L}_{ep}\] where \(\alpha\) balances the two pretraining tasks. In this work, we set \(\alpha=0.5\). After pretraining, the validation accuracies for structure-aware masked node modeling and edge prediction are \(82.27\%\) and \(95.77\%\), respectively.
| w/o KD | Area | Delay | ||||||
|---|---|---|---|---|---|---|---|---|
| 2-5(lr)6-9 | MAE\(\downarrow\) | MAPE\(\downarrow\) | \(R^{2}\) \(\uparrow\) | RRSE\(\downarrow\) | MAE\(\downarrow\) | MAPE\(\downarrow\) | \(R^{2}\) \(\uparrow\) | RRSE\(\downarrow\) |
| Graph-Based Baselines | ||||||||
| Graph-XGBoost | 0.9267 | 0.19 | 0.3987 | 0.7754 | 0.6384 | 0.12 | 0.3362 | 0.8147 |
| Graph-GNN | 0.5497 | 0.09 | 0.5857 | 0.6437 | 0.7327 | 0.13 | 0.6639 | 0.5797 |
| LLM-Based Baselines | ||||||||
| CodeV-DS-6.7B | 0.8967 | 0.17 | 0.4862 | 0.6973 | 0.6403 | 0.12 | 0.3905 | 0.7807 |
| CodeV-CL-7B | 0.7982 | 0.15 | 0.5755 | 0.6515 | 0.5620 | 0.10 | 0.5174 | 0.6947 |
| CodeV-QW-7B | 0.7229 | 0.13 | 0.6353 | 0.6039 | 0.5340 | 0.09 | 0.5277 | 0.6872 |
| Ours | ||||||||
| StructRTL (w/o \(\mathcal{L}_{mnm}\)) | 0.3900 | 0.07 | 0.7249 | 0.5245 | 0.5730 | 0.11 | 0.7473 | 0.5027 |
| StructRTL (w/o \(\mathcal{L}_{ep}\)) | 0.4035 | 0.07 | 0.7018 | 0.5460 | 0.5902 | 0.11 | 0.7368 | 0.5130 |
| StructRTL | 0.3649 | 0.06 | 0.7463 | 0.5037 | 0.5414 | 0.10 | 0.7630 | 0.4868 |
3.4 Quality Estimation↩︎
After pretraining, StructRTL outputs structure-informed embeddings ready for RTL design quality estimation. This task is formulated as a regression problem, where node-level embeddings are first aggregated into a graph-level representation using joint mean and max pooling. The resulting graph embedding is then passed through a 3-layer MLP to predict quality metrics such as area and delay. Given that these metric values have large magnitudes and exhibit significant variance across designs, we apply the logarithm transformation to these values to make the target distribution more suitable for model learning. This transformation does not affect the practical performance of the model, as we are more concerned with the relative quality of different designs. For this task, we use the log-cosh loss [31], which is robust to outliers, and denote the loss function as \(\mathcal{L}_{qe}\).
For evaluation, we use four standard regression metrics: mean absolute error (MAE), mean absolute percentage error (MAPE), coefficient of determination (\(R^{2}\)), and root relative squared error (RRSE). Given predicted values \(\hat{y_{i}}\) and ground truth values \(y_{i}\) for \(i \in \left[1,N\right]\), these metrics are defined as: \[\begin{align} \text{MAE} &= \frac{1}{N} \sum_{i=1}^{N} \left| \hat{y}_i - y_i \right| \\ \text{MAPE} &= \frac{1}{N} \sum_{i=1}^{N} \left| \frac{\hat{y}_i - y_i}{y_i} \right| \\ R^2 &= 1 - \frac{\sum_{i=1}^{N} (\hat{y}_i - y_i)^2}{\sum_{i=1}^{N} (y_i - \bar{y})^2} \\ \text{RRSE} &= \sqrt{\frac{\sum_{i=1}^{N} (\hat{y}_i - y_i)^2}{\sum_{i=1}^{N} (y_i - \bar{y})^2}} \end{align}\] where \(\bar{y}\) denotes the mean of the ground truth values.
3.5 Knowledge Distillation↩︎
Directly estimating quality metrics from the RTL stage can be challenging, as there remains a significant gap between RTL designs and the PM netlists from which area and delay are actually measured. To bridge this gap, we incorporate a knowledge distillation (KD) strategy that transfers low-level insights from PM netlists into the CDFG predictor. As illustrated in Figure 5, we synthesize and map RTL designs into PM netlists using Yosys [24] and ABC [32] with the SkyWater 130nm technology library [33]. We then extract area and delay metrics from the resulting netlists. To model the PM netlist, we initialize each cell’s embedding with a concatenation of its one-hot cell type encoding, logic truth table, and associated area and pin delay information. These embeddings are processed using a GIN, followed by joint mean and max pooling to obtain a graph-level representation, which is then passed to a 3-layer MLP for quality estimation. Since the area and delay values are derived directly from these netlists, the quality prediction at this stage is naturally more accurate than at the RTL level. To improve RTL-stage predictions, we perform KD by aligning the final-layer activations of the CDFG predictor \(z_{\text{CDFG}}^{-1}\) with those of the PM predictor \(z_{\text{PM}}^{-1}\). The KD loss is defined as: \[\mathcal{L}_{kd} = \tau \cdot \mathcal{L}_{cos}(z_{\text{CDFG}}^{-1}, z_{\text{PM}}^{-1}) + (1 - \tau) \cdot \mathcal{L}_{mse}(z_{\text{CDFG}}^{-1}, z_{\text{PM}}^{-1})\] where \(\mathcal{L}_{cos}\) is the cosine similarity loss, \(\mathcal{L}_{mse}\) is the mean squared error (MSE) loss, and \(\tau\) balances the contribution of the two terms. We set \(\tau=0.7\) in our experiments. This alignment encourages the CDFG predictor to internalize fine-grained low-level insights learned from the gate-level view, thereby improving its quality estimation performance.
During training, we first train the PM predictor and freeze its parameters. It is then used to guide the learning of CDFG predictor. The total loss for training the CDFG predictor is: \[\mathcal{L}_{total} = \mu\mathcal{L}_{qe} + (1 - \mu)\mathcal{L}_{kd}\] where we set \(\mu=0.5\) in our experiments. Note that the PM predictor is only used during training for supervision; during validation, only the CDFG predictor is retained.
4 Experiments↩︎
| w/ KD | Area | Delay | ||||||
|---|---|---|---|---|---|---|---|---|
| 2-5(lr)6-9 | MAE\(\downarrow\) | MAPE\(\downarrow\) | \(R^{2}\) \(\uparrow\) | RRSE\(\downarrow\) | MAE\(\downarrow\) | MAPE\(\downarrow\) | \(R^{2}\) \(\uparrow\) | RRSE\(\downarrow\) |
| Teacher | ||||||||
| PM Predictor | 0.2982 | 0.05 | 0.9334 | 0.2581 | 0.1688 | 0.03 | 0.9484 | 0.2272 |
| Graph-Based Baselines | ||||||||
| Graph-XGBoost | 0.6333 | 0.12 | 0.6813 | 0.5645 | 0.4676 | 0.08 | 0.5910 | 0.6395 |
| Graph-GNN | 0.4689 | 0.09 | 0.7954 | 0.4523 | 0.2926 | 0.05 | 0.8113 | 0.4344 |
| LLM-Based Baselines | ||||||||
| CodeV-DS-6.7B | 0.4896 | 0.09 | 0.7928 | 0.4552 | 0.3787 | 0.07 | 0.7235 | 0.5258 |
| CodeV-CL-7B | 0.4192 | 0.08 | 0.8225 | 0.4213 | 0.3208 | 0.06 | 0.7696 | 0.4800 |
| CodeV-QW-7B | 0.4397 | 0.08 | 0.8174 | 0.4273 | 0.3284 | 0.06 | 0.7687 | 0.4809 |
| Ours | ||||||||
| StructRTL (w/o \(\mathcal{L}_{mnm}\)) | 0.4015 | 0.07 | 0.8557 | 0.3799 | 0.2446 | 0.04 | 0.8796 | 0.3470 |
| StructRTL (w/o \(\mathcal{L}_{ep}\)) | 0.4071 | 0.07 | 0.8480 | 0.3899 | 0.2568 | 0.04 | 0.8654 | 0.3669 |
| StructRTL | 0.3856 | 0.07 | 0.8676 | 0.3639 | 0.2381 | 0.04 | 0.8872 | 0.3359 |
In this section, we conduct extensive experiments to show the effectiveness of our proposed framework, StructRTL. We begin by introducing the baselines, experimental settings, and dataset construction process. We then report comparative results on post-synthesis area and delay prediction tasks. Additionally, we perform an ablation study to demonstrate the importance of the two pretraining tasks in learning structure-informed representations.
4.1 Baselines↩︎
In this work, we primarily compare StructRTL with VeriDistill [12], a recent state-of-the-art method that leverages LLMs specifically trained for Verilog generation [9]–[11] to derive embeddings from RTL code. VeriDistill has shown strong performance on RTL design quality estimation tasks over a large-scale dataset of more than 10,000 designs. Following their setup, we adopt the open-source Verilog LLM CodeV [10], which includes three variants: CodeV-DS-6.7B, CodeV-CL-7B, and CodeV-QW-7B, finetuned from DeepSeek-Coder [34], CodeLlama [35], and CodeQwen [36], respectively. These models process the RTL code as raw token sequences, generate token-level embeddings, and apply mean pooling followed by a 3-layer MLP to produce final quality predictions. In addition, we implement two graph-based baselines following prior work [4]. First, we implement Graph-XGBoost, where we extract hand-crafted statistical features from the CDFG, including the total bits per node type, the frequency of each node type, the average wire width, and the length of the longest combinational logic path. These features are concatenated and fed into an XGBoost [14] regressor, following the configuration described in their original work. Second, we implement Graph-GNN, which uses a GNN to directly process the CDFG without any self-supervised pretraining. The resulting node embeddings are aggregated via joint mean and max pooling and passed through a 3-layer MLP for quality estimation. This setup mirrors the architecture used in our PM predictor, with further details about the model presented in the following subsection.
4.2 Experimental Setup↩︎
In this subsection, we detail the model configurations and training parameters. StructRTL uses an 8-layer GIN, with an 8-layer Transformer encoder, each layer containing 4 attention heads. The model is trained for 2,000 epochs with a batch size of 16, using the AdamW [37] optimizer with a learning rate of 2e-5 and weight decay of 1e-4. The PM predictor employs a 20-layer GIN with residual connections, trained for 1,000 epochs with a batch size of 256. It is optimized with the Adam [38] optimizer at a learning rate of 1e-4 and weight decay of 1e-5. The 3-layer MLP quality estimators are trained for 600 epochs with a batch size of 256, using the same optimizer settings as the PM predictor. All models have been trained until full convergence. Experiments are conducted on a cluster of 5 L40 GPUs, each with 46GB of memory. For further details, please refer to our code implementation provided in the Appendix.
4.3 Dataset Construction↩︎
For dataset construction, we begin by collecting some existing Verilog datasets, including VeriGen [39], and DeepCircuitX [40], which are sourced from open-source GitHub repositories and textbooks. We filter out designs that cannot be converted into CDFGs or synthesized into PM netlists. Additionally, we use Verilator [41] to simulate these designs with randomly generated input patterns, retaining only those with meaningful outputs. This ensures that the post-synthesis area and delay values are well-defined. The resulting dataset consists of 13,200 designs, which is split into training and validation sets with a ratio of 0.8:0.2. For further details on the dataset statistics and label distribution, please refer to the Appendix.
4.4 Experimental Results↩︎
In this subsection, we present a comparative analysis of post-synthesis area and delay prediction between StructRTL and baseline methods. Among all evaluation metrics, we primarily focus on the \(R^{2}\) score, as it provides insight into the relative quality of two designs, which is crucial for guiding optimization efforts. As shown in Table 1, StructRTL significantly outperforms both graph-based and LLM-based baselines without incorporating the knowledge distillation strategy, achieving a 0.1 increase in the \(R^{2}\) score over the previous state-of-the-art methods for both area and delay prediction. Notably, Graph-XGBoost performs the worst among all methods, highlighting the limited expressiveness of hand-crafted features. Compared to Graph-GNN, which performs quality estimation in an end-to-end manner, StructRTL demonstrates superior performance, underscoring the effectiveness of structure-aware graph self-supervised learning. This approach helps the model learn structure-informed representations that are suitable and generalizable for downstream quality estimation tasks. Besides, StructRTL shows a significant advantage over LLM-based baselines, especially in the delay prediction task. This is primarily due to the fact that, unlike the token-based view, the CDFG exposes the design’s structural semantics more explicitly, providing richer cues for learning complex patterns that impact the design’s quality. This is particularly important for delay prediction, which is closely tied to the design’s structure. Table 2 presents the results when the knowledge distillation strategy is incorporated. As shown, knowledge distillation improves the performance of all methods, highlighting the importance of cross-stage supervision. However, StructRTL consistently achieves the best results, further validating the effectiveness of structural learning. While there remains a gap between StructRTL and the PM predictor, StructRTL’s performance is highly encouraging, motivating further research in RTL design quality estimation.
Ablation Study. We conduct an ablation study to assess the impact of the two pretraining tasks in StructRTL. Specifically, we remove the structure-aware masked node modeling and edge prediction, resulting in two variants: StructRTL (w/o \(\mathcal{L}_{mnm}\)) and StructRTL (w/o \(\mathcal{L}_{ep}\)). As shown in Tables 1 and 2, removing either task leads to performance degradation, demonstrating the importance of both tasks in learning the structure-aware representations necessary for accurate RTL design quality estimation.
5 Conclusion↩︎
In this work, we introduce StructRTL, a novel structure-aware graph self-supervised learning framework to improve RTL design quality estimation. By leveraging CDFG, StructRTL incorporates two tailored pretraining tasks, structure-aware masked node modeling and edge prediction, to learn structure-informed representations for downstream quality estimation. StructRTL outperforms prior methods that either rely on shallow hand-crafted features or fail to capture the structural semantics of RTL designs. To further boost performance, we integrate a knowledge distillation strategy that transfers low-level insights from PM netlists into the CDFG predictor, enabling StructRTL to achieve state-of-the-art results in area and delay prediction. Our findings highlight the effectiveness of combining structural representation learning with cross-stage supervision and open new directions for advancing RTL design quality estimation in EDA workflows.
6 Appendix↩︎
6.1 Code Implementation↩︎
The implementation of StructRTL and the training/evaluation datasets are available in the anonymous GitHub repository: https://anonymous.4open.science/r/StructRTL-CB09/.
6.2 CDFG Details↩︎
In the “CDFG Construction" subsection of the main submission, we describe the process of constructing the CDFG. In this section, we provide additional details, including a list of all node types along with their respective counts, ratios, and descriptions in our dataset, as shown in Table 4. The CDFG contains a total of 32 distinct node types, with significant variation in their frequencies. For instance, Wire nodes are the most common, comprising 40.05% of the dataset, while Unary Operator nodes, such as LNot and Not, make up a small portion of the dataset, with frequencies as low as 0.00% to 1.18%. For the structure-aware masked node modeling pretraining task, we formulate it as a 32-class classification problem. From Table 4, we can observe a severe class imbalance, particularly with the operation node types, which are underrepresented compared to storage elements such as Wire and Register nodes. To mitigate this issue, we propose two strategies: stratified masking and class-balanced focal loss, which are described in the”Pretraining Tasks" subsection of the main submission.
| Range | Count |
|---|---|
| \(\left[0,600\right)\) | 10645 |
| \(\left[600, 5000\right)\) | 1148 |
| \(\left[5000, 10000\right)\) | 542 |
| \(\left[10000, 15000\right)\) | 497 |
| \(\left[15000, 20000\right)\) | 368 |
| Node Type | Count | Ratio | Description | |
|---|---|---|---|---|
| Unary Operator | LNot | 33521 | 1.18% | Logical NOT |
| Not | 24579 | 0.86% | Bitwise NOT | |
| URxor | 119 | 0.00% | Unary reduction XOR | |
| URand | 739 | 0.03% | Unary reduction AND | |
| URor | 5285 | 0.19% | Unary reduction OR | |
| Binary Operator | Lt | 2852 | 0.10% | Less than |
| Le | 2285 | 0.08% | Less than or equal | |
| Gt | 1701 | 0.06% | Greater than | |
| Ge | 3139 | 0.11% | Greater than or equal | |
| Add | 30179 | 1.06% | Addition | |
| Sub | 6177 | 0.22% | Subtraction | |
| Mul | 3325 | 0.12% | Multiplication | |
| Div | 198 | 0.01% | Division | |
| Mod | 142 | 0.00% | Modulo operation | |
| ShiftLeft | 261 | 0.01% | Logical left shift | |
| ShiftRight | 487 | 0.02% | Logical right shift | |
| And | 29679 | 1.04% | Logical AND | |
| Or | 8303 | 0.29% | Logical OR | |
| Eq | 189418 | 8.17% | Equality | |
| Neq | 1350 | 0.05% | Inequality | |
| BitAnd | 51656 | 1.82% | Bitwise AND | |
| BitOr | 23330 | 0.82% | Bitwise OR | |
| BitXor | 101147 | 3.56% | Bitwise XOR | |
| BitNXor | 67 | 0.00% | Bitwise XNOR | |
| N-ary Operator | PartSelect | 124144 | 4.36% | Bit-range extraction |
| Concat | 52727 | 1.85% | Bitwise concatenation | |
| Cond | Cond | 571656 | 20.09% | Ternary conditional operator |
| Wire | Wire | 1139415 | 40.05% | Wire declaration or reference |
| Const | Const | 232450 | 8.17% | Constant literal value |
| I/O | Input | 73853 | 2.60% | Input port |
| Output | 64047 | 2.25% | Output port | |
| Reg | Reg | 66680 | 2.34% | Register declaration |
6.3 Dataset Statistics↩︎
In this section, we provide additional details on the dataset statistics and label distributions. Our dataset consists of 13,200 designs, with the number of nodes in the CDFG ranging from 4 to 19,169. Table 3 presents a coarse-grained distribution of node counts across the entire dataset, revealing that the majority of designs contain fewer than 600 nodes. To provide a closer look at this majority subset, Figure 6 shows a more fine-grained distribution of node counts specifically for designs with fewer than 600 nodes in the CDFG.
Figure 7 illustrates the distributions of post-synthesis area and delay values across all designs in the dataset. Given the large magnitudes and significant variance of these metrics, we apply a logarithmic transformation to normalize the target distributions and facilitate more effective model training. This transformation does not impact practical model performance, as our primary focus lies in capturing the relative quality of different designs rather than their absolute values.