1 Introduction↩︎

Scientific simulation powered by high-performance computing (HPC) enables accurate modeling of complex phenomena in climate science, physics, biology, and cosmology [1]–[7]. However, modern simulations routinely generate petabyte-scale data, such as CMIP climate outputs [8] and large fluid dynamics runs [9]. Storing and moving these data stresses shared I/O and network resources [10]–[14], making efficient data compression essential for scalable scientific workflows.

Lossless compressors [15]–[18] typically provide only limited compression ratios on scientific data [19]. Error-bounded lossy compressors [20]–[27] achieve much higher ratios by exploiting local correlations through predictors such as curve fitting [21] and spline interpolation [28]. Yet these closed-form predictors can miss irregular data features. Recent neural-hybrid methods therefore integrate DNN predictors [29]–[35] to improve compression quality while preserving error bounds.

Despite their algorithmic benefits, neural-hybrid compressors are difficult to run efficiently on general-purpose platforms. CPU-only systems lack the throughput and parallelism needed for modern data rates [36]–[38]; GPU-only systems accelerate neural operators but underutilize resources on sequential and memory-bound non-neural stages; and CPU-GPU pipelines suffer from PCIe transfers between neural and non-neural components. These mismatches motivate customized hardware support [39].

While an application-specific ASIC appears to be a natural solution to the limitations of general-purpose processors, a naive implementation of neural-hybrid lossy compression faces significant challenges. First, the level-wise predictor introduces a memory-bound bottleneck due to irregular access patterns and extensive intermediate data that saturate on-chip buffers and exert excessive pressure on off-chip bandwidth. Second, the absence of inter-stage pipelining leads to severe idle cycles, as each module – predictor, neural network, and lossless codec – must wait for its predecessor to finish before commencing execution. Third, fixed-function datapaths hinder scalability, making it difficult to adapt to varying data sizes and workloads without costly hardware redesign.

To overcome these limitations, we propose FLARE, a dataflow-aware and scalable hardware architecture for neural-hybrid scientific lossy compression. FLARE introduces look-ahead computation ordering to reduce intermediate buffering and off-chip DRAM accesses, slice-wise normalization with operator fusion to remove global-normalization stalls and redundant memory movement, and a dataflow-aware scalable design to coordinate prediction, neural processing, and lossless coding through hybrid pipelined-parallel execution. To our knowledge, FLARE is the first scalable hardware architecture for neural-hybrid scientific lossy compression, achieving \(3.50\times\)–\(96.07\times\) runtime speedups and \(24.51\times\)–\(520.68\times\) energy-efficiency gains.

2 Background and Motivation↩︎

2.1 Neural-Hybrid Lossy Compression↩︎

The state-of-the-art neural-hybrid lossy compressor, NeurLZ [35], builds on SZ3 [27] by combining interpolation-based prediction, quantization, lossless coding, and lightweight neural operators, as shown in Figure 1. During compression, NeurLZ performs level-wise, block-based iterative interpolation (Figure 3); each prediction error is quantized, the quantization code is entropy-coded, and the reconstructed value is reused as a reference for later levels. After conventional reconstruction, the full data are globally normalized and processed by the neural module for online feature learning. Decompression reverses this flow: quantization codes are decoded, values are iteratively reconstructed, and the globally normalized reconstruction is refined by the stored neural model.

2.2 Analysis of General Hardware↩︎

General-purpose CPUs and GPUs poorly match NeurLZ’s hybrid workload, which mixes control- and memory-bound non-neural stages with parallel neural computation. We evaluate three configurations on the platforms in Table 1: CPU-only, which preserves compression quality but lacks neural parallelism; GPU-only, which uses cuSZ [37] for non-neural stages and gives the shortest runtime but lower compression ratios; and CPU-GPU, which keeps high compression quality but suffers from PCIe transfers. On Hurricane at Plat-2, PCIe communication takes 18% and 22% of compression and decompression time, respectively. The compression ratios of CPU-only, GPU-only, and CPU-GPU are 387\(\times\)/25\(\times\)/387\(\times\) on Miranda, 16,000\(\times\)/31\(\times\)/16,000\(\times\) on Nyx, and 20\(\times\)/16\(\times\)/20\(\times\) on Hurricane; runtimes are shown in Figure 2.

2.3 Challenges for Customized Hardware↩︎

Customized hardware can exploit NeurLZ’s structure, but a naive design faces three challenges.

The workload is fundamentally memory bounded: level-wise block interpolation repeatedly reads and writes reconstructed data across levels, multidimensional interpolation creates irregular strides in linear memory, and global normalization adds two full-data sweeps. As shown in Figure 2, non-neural components in Hurricane decompression require only \(0.23\%\) of the neural FLOPs but still consume nearly 2\(\times\) latency, indicating that data movement dominates. Buffering all intermediate data on chip would require impractical SRAM capacity for large scientific datasets.

Bubble overhead arises due to the global normalization process, which prevents the system from maintaining a fully pipelined execution. Although partial quantized errors can be forwarded to the lossless encoder for efficient pipelining, global normalization requires access to the entire reconstructed dataset. This dependency delays the neural network, which processes data at a fine-grain two-dimensional slice level, until normalization is finished, thereby substantially reducing pipeline efficiency.

Limited scalability in fixed-function datapaths hinders efficient handling of diverse data sizes and workloads. Over-provisioned designs lead to unnecessary silicon area and energy overhead, while under-provisioned ones fail to meet latency constraints.

These challenges underscore the need for a more efficient, scalable, and dataflow-aware architecture to support neural-enhanced lossy compression at scale.

3 Proposed Hardware: FLARE↩︎

3.1 Look-ahead Computation Order↩︎

To address intensive and irregular memory accesses under limited on-chip SRAM, we propose a look-ahead computation order that reduces the SRAM required for intermediate results while preserving algorithmic efficiency. The key idea is to exploit the data locality of the level-wise block-based interpolation procedure by reordering execution to maximize the reuse of reconstructed data. Since interpolation operations are independent across blocks, partial block-granularity computation can span multiple levels, allowing later levels to start before the current level is fully completed. As a result, the smaller intermediate results of partially processed blocks can be buffered in SRAM and reused early, avoiding expensive off-chip memory transactions. Once locality at Level-1 has been fully exploited, these partial results are directly forwarded to downstream modules because they are no longer needed for subsequent interpolation.

Figure 4 illustrates the proposed look-ahead strategy. At each level, half of the newly reconstructed blocks are immediately forwarded to the next level, while the remaining half is deferred until the first half completes processing at Level-1 and produces partial final results. For example, the lower half of the blocks reconstructed at Level-3 is first processed at Level-2 (step 2), whereas the upper half is processed later at step 5 after the lower half has been computed through Level-1. Because Level-1 results are not needed for subsequent interpolation, this approach reduces the SRAM capacity requirement by 3.46\(\times\) for a fixed block size of \(32 \times 32 \times 32\) with 32-bit values, as shown in Figure 6. In contrast, the original computation order requires the entire dataset to be stored in SRAM to avoid excessive off-chip memory accesses, which becomes impractical for large-scale scientific datasets.

Essentially, the proposed look-ahead computation order adopts a Depth-First Exploration strategy – a recursive traversal that processes data blocks in a depth-first manner, producing partial results early in the computation. Unlike the original Breadth-First Exploration approach, which fully processes all blocks at each level before proceeding to the next, our depth-first approach enables an efficient execution order that exploits data locality to eliminate redundant data accesses, minimize memory usage, and enhance overall performance. By processing blocks across levels in an out-of-order fashion, the proposed algorithm effectively manages memory resources and reduces latency, making it particularly suitable for high-performance computing applications.

3.2 Slice-wise Normalization with Operator Fusion↩︎

Global normalization in the neural component scales and centers the data before neural network processing, but it requires repeated full-dataset traversals, causing redundant memory accesses and pipeline bubbles. To address this, we propose slice-wise instance normalization, which operates directly on two-dimensional data slices. This approach matches the neural network’s slice-based execution pattern and enables fine-grained pipelined dataflow. Each normalized slice can then be streamed directly to the neural component on the fly, eliminating the overhead of global normalization across the entire dataset.

We further reduce memory accesses by fusing normalization with the first convolution kernel. Specifically, we use \(max_i\) and \(min_i\) to track the maximum and minimum values of the \(i\)-th slice during prediction. Embedding normalization into the convolution eliminates the separate read and write operations for normalized data. For each data point \(D[x,y,i]\) in the \(i\)-th slice, the normalized value is computed as: \[D_N[x,y,i] = \frac{D[x,y,i] - min_i}{max_i - min_i} \label{equ:norm}\tag{1}\] where \(D_N[x,y,i]\) denotes the normalized data. Integrating this normalization into the computation of the first convolution layer yields the convolution output \(O[x, y, o]\): \[\begin{align} &O[x, y, o] \notag \\ &= \sum_{k_x,k_y} D_N[x + k_x, y + k_y, i] \cdot W[k_x, k_y, o] + b[o] \\ &= \sum_{k_x,k_y} \frac{D[x + k_x, y + k_y, i] - min_i}{max_i - min_i} \cdot W[k_x, k_y, o] + b[o] \\ &= \sum_{k_x,k_y} D[x + k_x, y + k_y, i] \cdot W'[k_x, k_y, o] + b'[o] \end{align}\] where the updated convolution weight \(W'[k_x, k_y, o]\) and bias \(b'[o]\) incorporate the normalization parameters and are computed as: \[\begin{align} &W'[k_x, k_y, o] = \frac{W[k_x, k_y, o]}{max_i - min_i} \\ &b'[o] = b[o] - \sum_{k_x,k_y} \frac{min_i}{max_i - min_i} \cdot W[k_x, k_y, o] \end{align}\]

Compared to explicitly computing \(D_N[x, y, i]\), updating the convolution kernel \(W'[k_x, k_y, o]\) and \(b'[o]\) introduces minimal additional workload due to the small size. Furthermore, the compression quality achieved by the proposed instance normalization remains comparable to that of the original global normalization, as analyzed in Section 4.1.

3.3 Dataflow-Aware and Scalable Design↩︎

The proposed look-ahead computation order and slice-wise normalization allow reconstructed data normalization and quantized error generation to proceed at slice granularity. This enables the prediction modules (interpolation and quantization), lossless codec module, and neural network components in NeurLZ to execute under a hybrid dataflow that combines pipelined and parallel processing. During compression, the prediction modules generate a batch of slices at each time step, with the batch size determined by the block size. While subsequent slices are being computed, the current batch is dispatched downstream to the neural network and lossless codec module, forming a pipelined dataflow. At the same time, the neural network uses the reconstructed slices for error feature extraction, while the lossless codec, such as an entropy encoder, processes the quantized errors. This concurrent execution forms a parallelized dataflow. During decompression, the computation order is reversed: the dependency from Huffman decoding to data prediction creates a fine-grained pipelined dataflow across lossless decoding, prediction, and neural network inference. This hybrid execution pattern enables fine-grained processing in both compression and decompression, improving throughput and scalability.

To support this hybrid dataflow across diverse datasets and workloads, we propose a dataflow-aware, scalable FLARE Computing Core, as shown in Figure 5. The core integrates prediction, including interpolation and quantization, with neural network and lossless codec components. By keeping intermediate results on-chip, each component can operate on the fly, reducing costly off-chip data movement and improving throughput. Although each module is customized for its own computation and memory access pattern, the overall architecture remains modular and scalable across different data sizes and workload configurations.

The FLARE Computing Core consists of four components: (1) an on-chip SRAM buffer, (2) a Prediction Engine for interpolation and quantization, (3) a Neural Engine for neural network operations, and (4) a Codec Engine for lossless Huffman encoding and decoding.

The on-chip SRAM buffer provides high-bandwidth, low-latency temporary storage for intermediate data. It reduces off-chip DRAM accesses and supplies fast data access to the Prediction Engine for pipelined execution.

The Prediction Engine contains \(M\) one-dimensional (1D) systolic arrays, each processing interpolation and quantization for one data block. Each array performs matrix-vector multiplications with fixed interpolation coefficients, such as \((w_1, w_2, w_3)\) in cubic interpolation. A sliding-window mechanism streams neighboring anchor points through the processing elements (PEs), improving data reuse. Within each array, the interpolation error is computed by comparing the interpolated values with the original data and is then quantized for data reconstruction. Since blocks are independent, the engine can process up to \(M\) blocks in parallel.

The Neural Engine accelerates neural network operations using a two-dimensional (2D) PE array for workloads such as convolutions, matrix multiplications, and attention mechanisms. Its grid layout supports parallel processing across multiple data streams. A dedicated global buffer caches intermediate results locally to reduce DRAM traffic and sustain throughput during training or inference.

The Codec Engine uses ALU-based processing elements for control-intensive Huffman encoding and decoding. It is tightly integrated with the Prediction Engine so that quantized error values can be compressed or decompressed immediately.

As shown in Figure 7, during compression, outputs from the Prediction Engine are streamed slice-wise to both the Neural and Codec Engines for concurrent execution. Due to the look-ahead computation order, the Prediction Engine produces outputs at non-uniform intervals. To absorb this variability, two FIFO-based circular buffers, FIFO1 and FIFO2, temporarily store quantized errors and reconstructed data, respectively, maintaining the pipelined dataflow. A similar pipeline is applied during decompression.

The FLARE Computing Core scales along two dimensions. Data-size scalability is achieved by adjusting \(M\), the number of parallel systolic arrays in the Prediction Engine, to match the throughput of the Neural Engine for different input sizes. Workload scalability is achieved by scaling \(N\), the number of FLARE Computing Cores, so multiple datasets can be processed concurrently. Thus, the architecture can adapt to different data sizes and workload intensities without redesign.

4 Evaluation↩︎

4.1 Algorithm Performance Evaluation↩︎

We evaluate slice-based normalization in the NeurLZ framework by replacing global normalization with the method in Section 3.2. Experiments use Nyx, Miranda, and Hurricane (Table 2) with a uniform error bound of \(10^{-3}\) for SZ3, NeurLZ, and FLARE. Reconstruction quality is measured by PSNR.

As shown in Figure 8, slice-based normalization improves PSNR over SZ3 by 6–10 dB across datasets. Its initial PSNR is slightly below NeurLZ, but becomes comparable after 5–6 epochs, showing that localized normalization preserves compression quality.

4.2 Evaluation Setup for Architecture↩︎

Hardware configuration. We evaluate a single-core configuration (\(N = 1\)) with 32 MB SRAM, four 1D systolic arrays (\(M=4\)), 8 MB/32 MB FIFO buffers, and a \(128 \times 128\) Neural Engine with a 24 MB global buffer. Table 3 summarizes the parameters.

Simulation and CAD tools. We build a bit-accurate, cycle-accurate simulator and a verified Verilog RTL implementation. The RTL is synthesized with Synopsys Design Compiler in a 28 nm CMOS library at 1 GHz, placed and routed with Synopsys IC Compiler, and evaluated for dynamic/static power using PrimeTime PX with simulation-derived switching activity. Memory area and power are estimated with Cacti, and neural dataflow is optimized with TimeLoop [40]. The final design reports power and area.

Baseline and benchmarks. We use the same datasets and error bound as NeurLZ. Baselines include CPU-only, GPU-only, and CPU-GPU NeurLZ on the platforms in Table 1; the GPU-only baseline uses cuSZ [37].

4.3 Evaluation Result↩︎

Compression performance. We evaluate the compression performance of the proposed FLARE across all systems and platforms using the Nyx, Miranda, and Hurricane datasets. Although our method requires additional epochs to achieve the same PSNR as NeurLZ, it still delivers significant gains in both speed and energy, due to its optimized dataflow and architectural support. As shown in Figure 9, on Nyx we observe \(4.61\times\)–\(96.07\times\) runtime reduction and \(31.27\times\)–\(520.68\times\) energy efficiency improvement; on Miranda, \(5.75\times\)–\(81.48\times\) runtime reduction and \(33.54\times\)–\(441.65\times\) energy efficiency gains; and on Hurricane, \(3.50\times\)–\(68.16\times\) runtime reduction alongside \(24.51\times\)–\(369.45\times\) energy efficiency improvements. These results confirm that our design not only accelerates lossy compression but also substantially lowers energy consumption.

Decompression performance. FLARE also achieves promising results in decompression. Specifically, on Nyx dataset, it delivers \(4.69\times\)–\(37.96\times\) runtime speedups and \(38.11\times\)–\(247.47\times\) energy efficiency improvements; on Miranda, \(4.36\times\)–\(35.59\times\) runtime speedups and \(35.48\times\)–\(192.89\times\) energy efficiency gains; and on Hurricane, FLARE achieves \(4.90\times\)–\(37.04\times\) runtime speedups alongside \(35.02\times\)–\(200.78\times\) energy efficiency improvements. These consistent gains across diverse datasets and platforms highlight the generality and scalability of our architecture for both compression and decompression processes.

4.4 Ablation Study↩︎

Scalability of the architecture. The modular architecture is designed with scalability as a core principle, offering two dimensions of flexibility: data size scalability and workload scalability.

For data-size scalability, the architecture adjusts the number of 1D systolic arrays (\(M\)) within each FLARE Computing Core to support different input sizes. Increasing \(M\) allows a single core to process more data in parallel and reduce runtime. As shown in Figure 10, we evaluate the compression and decompression runtime of the Nyx dataset by scaling \(M\) from 1 to 8. Decompression time decreases clearly as \(M\) increases. However, compression speedup is less pronounced because the fully pipelined dataflow and neural network training make the Neural Engine the dominant bottleneck. For example, the runtime reaches its minimum at \(M=4\), and adding more systolic arrays brings little benefit.

For workload scalability, the architecture supports parallel execution across multiple FLARE Computing Cores (\(N\)), each independently processing a distinct dataset or task. This is useful for large-scale deployments where multiple workloads must run concurrently. We evaluate runtime while processing two Nyx datasets, one Miranda dataset, and one Hurricane dataset as \(N\) scales from 1 to 4. As shown in Figure 10, runtime consistently decreases with more cores. When scaling from \(N=3\) to \(N=4\), the two Nyx datasets become the dominant bottleneck, with runtime reaching 1.16 seconds for compression and 0.42 seconds for decompression.

These results demonstrate that the proposed architecture effectively scales along both data size and workload dimensions. The overall speedup depends on workload distribution and system bottlenecks—particularly those introduced by the neural network or dataset-specific characteristics.

Data movement reduction. To quantify the impact of the proposed architecture, we analyze internal data transfers within a single FLARE Computing Core, focusing on the Prediction, Neural, and Codec Engines as the main contributors during compression and decompression. In the Prediction Engine, look-ahead processing reuses intermediate results from on-chip SRAM, while the systolic arrays keep data local within processing elements. Across engines, the hybrid dataflow supports pipelined and parallel execution, reducing unnecessary off-chip communication. Operator fusion further removes separate memory accesses for slice-wise normalization and convolution. Together, these features reduce overall data movement by improving on-chip reuse.

As shown in Figure 11, the proposed architecture reduces data movement by up to \(10\times\)¹ across three datasets. Normalization contributes the largest share of the reduction (56%), followed by prediction (22%), neural network operations (11%), and lossless codec (11%). These results show the proposed design effectively reduces data movement across compression and decompression workloads.

5 Conclusion↩︎

This paper presents FLARE, a dataflow-aware and scalable hardware architecture for accelerating neural-hybrid scientific lossy compression. FLARE uses look-ahead computation to reduce SRAM usage and improve pipeline throughput, and fuses slice-wise normalization into convolution to reduce bubble overhead and data movement. The proposed FLARE Computing Core improves on-chip data reuse, supports efficient hybrid execution, and scales with both dataset size and workload volume. To our knowledge, this is the first customized design for scientific lossy compression that jointly addresses dataflow efficiency and architectural scalability. Experiments show clear latency and energy-efficiency improvements over state-of-the-art baselines.

References↩︎