1 Introduction↩︎

State-of-the-art large language models (LLMs) [1]–[5] have adopted the Mixture-of-Experts (MoE) architecture for its computational efficiency and strong performance across a range of tasks. The traditional Transformer block consists of a self-attention module followed by a dense feed-forward network (FFN) [6]. In contrast, MoE architectures replace this single FFN (Figure 1 (a)) with many identically sized FFNs, known as experts (Figure 1 (b)). A trainable neural network, known as a gate function, sparsely activates these experts by dynamically routing input tokens to the experts selected at runtime. This increase in model parameters due to more FFNs improves model quality without the corresponding increase in computational cost.

Communication overheads in MoE. As MoE model sizes grow, GPU memory constraints prevent hosting all experts on a single device. The standard practice is to distribute experts across multiple GPUs using expert parallelism (EP), which requires token routing via many-to-many communication primitives like AlltoAll [1], [3], [4], [7] (Figure 1 (c)). Another round of AlltoAll communication restores the permuted tokens processed by experts to their original order in the sequence. AlltoAll communication is challenging to optimize on GPU networks and is highly sensitive to straggler delays — a phenomenon where a single straggler GPU delays all others from making progress [8]. These communication operations can account for 68% of the total runtime [9], [10], causing GPUs to remain idle (Figure 2, top left).

Kernel launch overheads in MoE. To mitigate these communication bottlenecks, recent work pipelines computation with communication kernels (Figure 2, left middle). However, the effectiveness of these solutions is limited by the overhead of launching many kernels from the CPU. Specifically, existing implementations [11]–[14] launch a large number of kernels per a single layer pass (see Table 1). Frequent kernel launches negatively affect performance by: (1) creating non-deterministic kernel start times across GPUs, exacerbating straggler issues; (2) introducing unnecessary synchronization points, causing GPUs to wait on peers or the CPU before proceeding; and (3) incurring repeated global memory round trips at kernel boundaries. Although CUDA graphs [15] can partially mitigate the first issue in static workloads, they are incompatible with MoE’s dynamic expert routing patterns. Addressing the remaining issues requires novel solutions, which we provide in this work through complete kernel fusion and asynchronous device-initiated communication.

Our Contributions: distributed MoE in a single kernel. To overcome these fundamental inefficiencies in state-of-the-art MoE models, we develop FlashMoE a megakernel that integrates all MoE computation and communication tasks into a single persistent GPU kernel i.e., a kernel that remains active for the entirety of the MoE operator (Figure 2 bottom left). Instead of multiple kernel launches coordinated by the CPU, FlashMoE requires launching only one kernel, significantly reducing the involvement of the CPU. Within the fused kernel, FlashMoE implements a reactive programming model to achieve fine-grained parallelism and loosely coupled, non-blocking execution among tens of thousands of GPU threads.

r0.5

In-kernel Block scheduling and Tile parallelism. FlashMoE implements tile-level parallelism, meaning it partitions input token matrices into smaller, independent units called tiles, which are processed by blocks but managed (scheduled and constructed) by warps. We specialize every thread block, except one, as processors to perform compute. In addition, we designate a dedicated Operating System (OS) block (4 warps) to perform administrative tasks of (1) scheduling computational work to processors (scheduler), and (2) decoding computational tasks from messages received from other GPUs (subscriber). This design allows FlashMoE to dynamically assign tasks to GPU blocks based on readiness, ensuring that no GPU SM remains idle throughout the lifetime of the MoE operator. FlashMoE selects tile dimensions to maximize GPU arithmetic intensity while benefitting from a high-degree of parallelism.

Asynchronous and payload-efficient communication. By redesigning the MoE operator from the ground up, FlashMoE resolves fundamental inefficiencies inherent in the conventional MoE execution pipeline. One notable inefficiency is token padding during communication. To simplify programming complexity and due to symmetry constraints of collective communication APIs, existing implementations have to zero-pad token payloads to match predefined buffer sizes. This occurs when tokens are asymmetrically routed to experts, resulting in GPUs receiving much less than the expected capacity. However, these null payloads waste communication bandwidth, bloat data transfer latency and may lead to unnecessary computations on null matrices in some implementations. FlashMoE introduces payload-efficient communication by sending non-padded tokens only to GPUs with actively selected experts, conserving both communication and computational resources.

Technical challenges. Realizing the single-kernel design of FlashMoE required solving several technical challenges to achieve high performance: (1) lightweight computational dependency management; (2) navigating optimal SM occupancy configurations; (3) implementing in-device BLAS operations; (4) minimizing inter- and intra-device synchronization overheads; (5) implementing transfer-awareness by leveraging DMA over Unified Virtual Addressing (UVA) when available. In addressing these challenges, FlashMoE’s design presents a radical departure from traditional synchronous AlltoAll collectives, where GPUs exhibit significant idle time during layer execution. For device-initiated communication, FlashMoE uses NVSHMEM [18] to establish a global address space across all GPUs for Direct Memory Access (DMA) communication. For in-device BLAS, FlashMoE develops custom high-performance GEMM operations via CUTLASS [19].

Results. Our evaluations show that FlashMoE achieves 6\(\times\) latency speedup, 9\(\times\) higher GPU utilization, 4\(\times\) better weak scaling efficiency and 5.7\(\times\) increased throughput compared to state-of-the-art implementations. We project these performance gains becoming even better in multi-node scenarios, where inter-node communication occurs using lower bandwidth inter-node links (e.g., RDMA, Infiniband).

2 Motivation↩︎

Synchronous Communication. AlltoAll or AllGather communication as currently used in MoE frameworks is a synchronous collective operation, whose completion requires the participation of all involved GPUs. Here, disparities in processing speeds or kernel scheduling among GPUs induce a straggler effect detrimental (Figure 13) to (1) the collective operation’s performance and (2) E2E performance, as stalled GPUs cannot proceed to downstream dependent or independent tasks until the collective terminates. We expound on this problem in §8.

Kernel Launch Overhead. We compare the kernel launch overheads between FlashMoE and existing baselines. Table 1 shows the number of kernel launches during a single forward pass: FlashMoE launches exactly one persistent kernel, while the baselines launch up to 550 short-lived kernels to perform the same computation. Figure 3 provides a visual comparison using CUDA API traces captured by NSight Systems, illustrating the difference between FlashMoE and DeepEP. DeepEP exhibits many small CUDA API calls, with frequent stalls between individual operators, leading to increased GPU idle time (Figure 3 (a)). In contrast, FlashMoE maintains high GPU utilization by avoiding launch overhead and synchronization gaps—achieving 93.17% GPU utilization compared to 14% for DeepEP. See §4 for experimental results and §9 for a discussion of related work.

3 Fused MoE Kernel Design↩︎

Modern distributed MoE systems suffer from two limitations: (1) frequent many-to-many (AlltoAll or AllGather) collectives on the critical path, and (2) significant overhead from repeated kernel launches. We address these in FlashMoE, a fully fused MoE operator implemented as a single persistent GPU kernel. Unlike previous approaches [1], [10]–[13], [20]–[25], FlashMoE is the first solution to implement a completely fused Distributed MoE kernel, eliminating kernel launch overhead entirely by requiring only a single kernel launch (see Table 1).

Actor-based model. The design of FlashMoE is based on the actor model of concurrent computation [26]–[28]. We implement this model by specializing GPU thread blocks and warps into three distinct actor roles: (1) Processor (§13.1), (2) Subscriber (§13.3), and (3) Scheduler(§13.2). The Processor performs compute (GEMMs and element-wise operations) and tile communication. We use CUTLASS [19] as the underlying infrastructure for high-performance BLAS routines and NVSHMEM for kernel-initiated communication [18]. The Subscriber and Scheduler perform administrative functions. Specifically, the Scheduler assigns computational tasks to available thread blocks. Our key innovation is making the Scheduler both multithreaded, enabling high scheduling throughput, and work-conserving, ensuring consistently high GPU SM utilization. On the other hand, the Subscriber decodes tile packets from peer GPUs to task descriptors (§3.1). Of the \(N\) thread blocks on a GPU, we specialize \(N-1\) to adopt the Processor role. We specialize the last block as the Operating System (OS). Within this block, we specialize three warps for the Subscriber role and one warp for the Scheduler role. This split of thread blocks across actors is intentional: our goal is to use few resources for administrative tasks while reserving bulk of the resources for performing MoE computation tasks. Figure 4 summarizes the FlashMoE architecture and its constituent actors, while Algorithm 5 gives a very close translation of the system in code. Note that \(A \in \mathbb{R}^{S \times H}\) is the input token matrix; \(O \in \mathbb{R}^{S \times H}\) the output matrix; and \(X \in \mathbb{R}^{E\times H \times D}\) is a 3-D tensor of expert weights, where \(E\) denotes the number of local experts for the executing GPU, \(H\) is the embedding dimension, \(D\) is the FFN intermediate dimension and \(S\) is the sequence length. \(T_{\phi} \in \left(\mathbb{N}\times\mathbb{R}\right)^{E \times C}\) is a routing table data structure, where \(T_{\phi}\left( e, c\right) = (i, w)\) indicates that token \(i\) at slot \(c\) dispatches to expert \(e\). \(w\) is the combine weight (Equation 2 ) and \(C\) is expert capacity. The tuple structure of \(T_{\phi}\) is an implementation detail. \(G_{\phi} \in \mathbb{R}^{S \times E}\) captures the affinity scores produced by the gate (Equation 3 ). Inter-actor interactions in FlashMoE. FlashMoE decomposes MoE computation and communication at the granularity of a tile, a statically sized partition of a tensor, to achieve parallel execution and efficient overlap of tasks. Each tile maps to a discrete unit of work encapsulated by a task descriptor. The Subscriber decodes these task descriptors from the remote tile packets it receives. Concurrently, the Scheduler receives notifications about available tasks and dispatches them for execution to Processor actors that perform computations defined by these tasks, namely the feed-forward network (FFN) and expert-combine operations. Figure 6 show the chain of actor interactions, demonstrating how FlashMoE enforces DMoE functional dependencies.

Determining tile dimensions in FlashMoE. Selecting appropriate tile dimensions in FlashMoE is crucial to ensure efficient GPU utilization. An undersized tile underutilizes the GPU, while excessively large tiles create register pressure, causing performance-degrading register spills to local memory. After careful parameter sweeps, we choose tile dimensions of (128, 64). Our key insights are: increasing tile width significantly raises the register usage per thread, potentially triggering costly spills; increasing tile height without adjusting thread count increases workload per thread, harming performance. Raising the thread count per block beyond our fixed value of 128 threads reduces the number of concurrent blocks, negatively affecting SM occupancy. Larger thread-block sizes also increase overhead from intra-block synchronization (__syncthreads() barriers), further degrading performance. Thus, our chosen tile dimensions balance register usage, shared-memory constraints, and GPU occupancy to deliver optimal performance.

3.1 Task Abstraction for Computation↩︎

Computational operators. The FFN operator is a standard position-wise feed-forward network widely used in Transformer architectures [6], composed of two linear transformations separated by a nonlinear activation \(\phi\) (e.g., GELU or ReLU):

\[\label{eq:ffn} \small \textrm{FFN}(x) = W_2 \cdot \phi(x W_1 + b_1) + b_2\tag{1}\]

Here, \(W_1\) and \(W_2\) represent learnable weight matrices, and \(b_1\) and \(b_2\) are biases. The expert-combine operation, used in architectures like GShard [29] and DeepSeek [1], merges outputs from multiple experts by computing a weighted combination based on their affinity scores: \[\label{eq:combine1}\small \mathcal{C}_i = \sum\limits_{j = 1}^k g_{i, e}\tag{2}\] \[\label{eq:combine2}\small \mathbf{h}_i = \sum\limits_{j = 1}^k \frac{g_{i, e}}{\mathcal{C}_i}\cdot \mathbf{h}_i^k\tag{3}\]

In these equations, \(i \in {0, S - 1}\) represents an input token index, \(e = E_{i,k}\) identifies the \(k\)-th expert selected for token \(i\), and \(g_{i,e}\) is the affinity score indicating how relevant expert \(e\) is for token \(i\).

Unified task abstraction. We unify the FFN and combine operations under a common abstraction called a task. Tasks provide a uniform interface for communicating tile-level work among Subscribers, Schedulers, and Processors. Formally, a task descriptor \(t \in \mathcal{T}\) is defined as a tuple: \[\small t = (\mathcal{M}, \star, \phi)\]

where \(\mathcal{M}\) is a set of metadata (e.g., device ID, tile index), \(\star\) is a binary tensor operation (specifically, matrix multiplication \(\cdot\) or Hadamard product \(\odot\)), and \(\phi\) is an element-wise activation function (e.g., ReLU or identity).

We define a task \(t\) operating on input tensors \(A\), \(B\), \(D\), producing output tensor \(C\), as follows: \[\label{eq:task95def}\small \mathcal{F}_t(A, B, C, D) \mathrel{\vcenter{:}}= C \gets \phi\left(A \star_t B + D\right)\tag{4}\]

The operator \(\star_t\) (instantiated from \(\star\)) may behave differently depending on the task metadata \(\mathcal{M}\), and the result of \(A \star_t B\) is accumulated into \(D\). We provide an example of task metadata in §12.

In practice, we implement each task defined by Equation 4 as a single fused __device__ decorated function which the Processor (Algorithm 16) invokes at runtime. Fusion for \(t\) entails applying \(\phi\) and the succeeding addition operation to registers storing the results of the binary operator \(\star_t\). To illustrate its flexibility, we show how the FFN and expert-combine operations can be expressed using this task framework. Note that we omit the matrix multiplication symbol (\(\cdot\)) for simplicity. Also, \(\phi_1\) can be any activation function, while \(\phi_2\) is the identity function. The FFN is expressed as: \[\begin{gather} \small t_1 = (\mathcal{M}, \cdot, \phi_1), \quad t_2 = (\mathcal{M}, \cdot, \phi_2), \\ \small \mathcal{F}_{t_1}(A, B_1, C_1, D_1) \mathrel{\vcenter{:}}= C_1 \gets \phi_1\left(A B_1 + D_1\right), \\ \small \mathcal{F}_{t_2}(C_1, B_2, C_2, D_2) \mathrel{\vcenter{:}}= C_2 \gets \phi_2\left(C_1 B_2 + D_2\right). \end{gather}\] Whereas, the expert-combine operation is formalized as: \[\begin{gather} \small t_3 = (\mathcal{M}, \odot, \phi_2), \\ \small \mathcal{F}_{t_3}(A, S, C, C) \mathrel{\vcenter{:}}= C \gets \phi_2\left(A \odot S + C\right). \end{gather}\]

3.2 Symmetric Tensor Layout for Inter-GPU Communication↩︎

Within a single GPU device, the actors in FlashMoE communicate through the GPU’s memory subsystem. Specifically, the Scheduler and Subscriber actors exchange data via fast shared memory, while other actor pairs communicate through global memory. For communication across multiple devices, FlashMoE uses device-initiated communication, leveraging the one-sided PGAS (Partitioned Global Address Space) programming model [30]. However, achieving scalable and correct one-sided memory accesses in PGAS without costly synchronization is a known challenge [1], [31]. We address this challenge with a provably correct and scalable solution: a symmetric tensor layout \(L\), supporting fully non-blocking memory accesses. We define L as:
\[L \in \mathbb{R}^{P\times R \times B \times E \times C \times H}\] where: \(P\) is the expert parallel world size, \(R\) identifies communication rounds (i.e., two rounds, one for token dispatch and one for combine), \(B\) is number of staging buffers, \(E\) is the number of local experts, \(C\) is the upscaled expert capacity (§3.2.1) and \(H\) is the token embedding dimension. Our core insight to enable non-blocking communication is temporal buffering. Specifically, we overprovision memory for the underlying token matrix by at least \(2 \cdot r\) times, where \(r\) is the number of communication rounds in the dependency graph, and the factor of \(2\) accounts for separate buffers for incoming and outgoing data within each communication round. For MoE models, we have \(2 \cdot r = 4\). This modest increase in memory usage eliminates the need for synchronization during one-sided data transfers. Figure 7 (b) illustrates how cells within this symmetric tensor layout are indexed and used for Direct Memory Access (DMA) and Remote DMA (RDMA) operations. As Theorem 1 reinforces, this indexing scheme over \(L\) is the underlying mechanism that allows for fully non-blocking accesses eliding synchronization because all accesses are write conflict-free. See§ 10 for the proof.

To construct \(L\), we start from the original token buffer \(T \in \mathbb{R}^{S \times H}\), where \(S\) is the sequence length and \(H\) is the token embedding dimension. We first reorganize the sequence dimension \(S\) into three sub-dimensions representing the expert capacity (\(C\)), local expert slots (\(E\)), and the expert parallel world size (\(W\)), st: \[C \cdot E \cdot W = C \cdot E' = S', \quad\text{where}\quad S' \geq S \text{ and } E' \geq E_W\] In the typical case of uniform expert distribution (illustrated in Figure 7 (a)), we have \(S' = S\) and \(E' = E_W\), where \(E_W\) is the total number of experts in the model. Thus, the size of the token buffer is \(Size(T) = S' \cdot H\). In Figure 7 (a), each cell labeled \(E_i\) (with \(i \in \{0,\ldots,3\}\)) is a matrix of size \((C, H)\). Extending prior work [12], [29], we introduce additional temporal dimensions \(R\) (communication rounds) and \(B\) (staging buffers). Each communication round has two fixed staging slots: one for outgoing tokens and another for incoming tokens. Each slot, indexed by dimension \(P\), forms a tensor of shape \((S', H)\). Therefore, the tensor size \(Size(L)\) is generally at least four times the original token buffer size, becoming exactly four times larger in the case of uniform expert distribution. Empirically, we find \(Size(L) \approx 4 \cdot Size(T)\), contributing memory overhead \(\leq 2\)% of memory capacity for inference of popular models. We present a thorough breakdown in §11.

3.2.1 In-place Padding for Payload Efficiency↩︎

Due to the dynamic and uneven distribution of tokens in MoE dispatch [32], GPUs commonly receive fewer tokens than their predefined expert capacity. Current MoE frameworks [11] typically pad these buffers with null tokens before computation, unnecessarily increasing communication payloads and degrading performance. In contrast, we propose in-place padding, performing padding directly within the local symmetric tensor buffers and thus eliminating excess network communication.

As we show in Figure 7 (a) as a reference, each cell \(E_i\) is sized according to the expert capacity \(C\). We further align this capacity to ensure divisibility by the tile block size \(bM = 128\), guaranteeing safe and aligned memory reads by Processor threads consuming remote tokens. This in-place padding strategy slightly increases the memory footprint of \(L\), as described below: \[Size(L) \approx \begin{cases} 4 \cdot Size(T), & \frac{S}{E} \geq bM \\[1ex] 4 \cdot \frac{bM \cdot E}{S} \cdot Size(T), & \text{otherwise} \end{cases}\]

4 Evaluation↩︎

We implement (§14) and evaluate FlashMoE across five metrics: Forward Latency (§ 4.1), GPU Utilization (§ 4.2), Overlap Efficiency (§ 4.4), Throughput (§ 4.3), and Expert Scalability (§ 4.5). We run experiments on a server with 8 NVIDIA H100 80G GPUs interconnected via NVLink, 125 GB of RAM, and 20 vCPUs. We used PyTorch 2.6.0, CUDA 12.8, and Ubuntu 22.04. All experiments use MoE transformer models configured with 16 attention heads, an embedding dimension of 2048, and an FFN intermediate size of 2048. We apply Distributed Data Parallelism (DDP) and Expert Parallelism for all experiments. We execute only the forward pass over a single MoE layer and measure the average runtime of 32 passes after 32 warmup passes. We use top-2 routing with a capacity factor of 1.0. We compare FlashMoE against several state-of-the-art MoE systems: (1) Comet [12], (2) FasterMoE [14], (3) Megatron-CUTLASS [13], and (4) Megatron-TE: Megatron-LM with Transformer Engine [33]. Comet relies on cudaMemcpyPeerAsync [34], while FasterMoE and Megatron-LM use NCCL exclusively for communication.

Desiderata. We observe Comet exhibiting anomalously bad performance values at 8 GPUs, so we exclude their results from evaluations at 8 GPUs and only include for results at \(\leq\) 4 GPUs. We evaluate FlashMoE using FP32 precision whereas all baselines use FP16. We do so because (1) of incomplete fp16 tuning (§15) and (2) no baseline supports FP32. Note, this precision discrepancy disadvantages FlashMoE by doubling its communication volume and computational workload.

4.1 Forward Latency↩︎

We first measure the forward latency of FlashMoE across different sequence lengths on both 4 and 8 GPU setups (Figure 8). FlashMoE consistently outperforms all baselines, with especially notable improvements at longer sequence lengths. On 4 GPUs, it achieves up to 4.6x speedup over Megatron-TE at 16K tokens, and 2.6x over FasterMoE. The gains are even more pronounced at 8 GPUs where FlashMoE maintains low latency, exhibiting up to 6.4x speedup over baselines that degrade steeply due to increasing communication costs as token buffers increase proportionally.

4.2 GPU Utilization↩︎

To quantify GPU efficiency, we measure Streaming Multiprocessor (SM) utilization during the forward pass (Figure 9). FlashMoE achieves 93.17% average SM utilization, over 9x higher than FasterMoE (9.67%), 6.8x higher than DeepEP+Megatron-LM (13.55%) 4x higher than Megatron-TE (59.11%), and 2.2x higher than Comet (42.31%). This improvement stems from our fully fused kernel architecture and fine-grained pipelining of compute and communication tasks. By eliminating idle gaps due to kernel launches and enabling in-kernel task scheduling, FlashMoE ensures SMs remain busy with productive work throughout execution.

4.3 Throughput↩︎

As shown in Figure 10, FlashMoE scales linearly with GPU count, reaching 17.7 MTokens/s at 8 GPUs. This is over 5.7x higher than FasterMoE and 4.9x higher than Megatron-TE and Megatron-CUTLASS. Notably, these results are achieved despite FlashMoE operating entirely in FP32, while baselines use FP16. This indicates that FlashMoE’s design eliminates throughput bottlenecks not by exploiting lower precision, but by maximizing hardware utilization and eliminating host-driven inefficiencies.

4.4 Overlap Efficiency↩︎

We evaluate the extent to which FlashMoE overlaps communication and computation by measuring weak scaling efficiency as the number of GPUs increases (Figure 11 (b)). We note that most baselines fail to execute at a single GPU, hence why we use 2 GPUs as the reference point. We observe that Megatron-CUTLASS and Megatron-TE degrade significantly, with overlap efficiency dropping below 50% at \(\geq 4\) GPUs. FlashMoE gives up to 3.88x and 4x higher efficiency at 4 and 8 GPUs, respectively. Figure 11 (a) further illuminates this efficiency, as FlashMoE shows stable forward latency growth. These results corroborate that FlashMoE’s actor-based design and asynchronous data movement achieve near-ideal overlap.

4.5 Expert Scalability↩︎

We analyze how FlashMoE scales with increasing number of experts at fixed sequence length (T = 16K). Note that for the discussed plots, the number of experts on the x-axis is the total number across all GPUs. Each GPU gets 1/8th of this value. As seen in Figure 12, FlashMoE maintains low, uniform latency, as desired, even as the number of experts grows from 8 to 128. In contrast, baselines exhibit superlinear latency increases due to increased kernel launch overheads. FlashMoE outperforms these baselines by up to 4X at 4 H100s and 6.6X at 8 H100s, both at 128 experts. FlashMoE’s payload-efficient communication and scheduler-driven in-kernel dispatching allow it to sustain expert parallelism without incurring the communication and orchestration penalties seen in other systems. These results reinforce FlashMoE’s scalability for ultra-sparse MoE configurations.

5 Limitations and Future Work↩︎

Engineering complexity. Fully fused, persistent kernels demand deep GPU + distributed-systems expertise; future work may investigate compiler/DSL abstractions to lower this barrier.

FP16 inefficiency. Our FP16 path is suboptimal (§15) due to insufficient tuning. We anticipate addressing this gap with autotuned GEMM operators like cuBLASDx [35] or CUTLASS builders.

Training support. This work targets inference; enabling training will require fusing backward computation and gradient communication with new bookkeeping and task descriptors.

6 Conclusion↩︎

We introduce FlashMoE, the first work to fuse the entire Distributed MoE operator into a single persistent GPU kernel that unifies computation, communication, and scheduling via actor-style concurrency, warp specialization, and async (R)DMA. We address two dominant bottlenecks in prior systems—CPU-managed synchronous communication and fragmented multi-kernel execution. Empirically, FlashMoE achieves up to 6× speedup, 9× higher GPU utilization, and 5.7× throughput for distributed MoE. Looking ahead, we see a shift from CPU orchestration to fully autonomous, GPU-native pipelines—extending this fusion approach to training and beyond.

7 Acknowledgements↩︎

This research is supported by NSF Award #2444537 and ACE, one of the seven centers in JUMP 2.0, a Semiconductor Research Corporation (SRC) program sponsored by DARPA. This work also used resources of the National Energy Research Scientific Computing Center, a DOE Office of Science User Facility supported by the Office of Science of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231 using NERSC award ASCR-ERCAP0030076. We acknowledge and thank Dr. Giulia Guidi for providing access to these NERSC supercomputing resources.

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8 Supplementary Motivation↩︎

In Figure 14, we present empirical cumulative and raw distributions of AlltoAll kernel runtime from distributed training of a 1.3B GPT-3 MoE model across 32 A100 and 8 V100 GPUs. We use this result to motivate the severity and prevalence of straggler effects. In Figure 14 (b), we observe P95 communication performance degradation of 1.32X when compared to the mean actual kernel time. This performance reduction is rather tame as the underlying hardware is a supercomputer well-tuned against “software jitter” [36]. However, we observe a more severe p95 performance loss of 11X in a single-node Virtual Machine (VM). In line with prior HPC works [37], [38], we argue that obviating the inherent barrier in this synchronous collective communication would allow GPUs to repurpose this observed idle time for downstream computation as depicted in Figure 13.

9 Related Work↩︎

Computation-Communication Overlap and Kernel Fusion. To reduce the communication overheads of synchronization in distributed DNN training, many research efforts have been focused on increasing the overlap of computation and communication. For generic Transformer-based models without MoE layers, many works [39]–[47] have provided insights and techniques to partition and schedule computation and communication operations, aimed at finer-grained overlapping. To address the challenges posed by AlltoAll communication and expert parallelism in MoE training, Tutel [48] and FasterMoE [14] overlap AlltoAll with expert computation. Lancet [49] additionally enables both non-MoE computation in forward pass and weight gradient computation in backward pass to be overlapped with AlltoAll. Despite overlapping, the performance of these approaches is limited in practice due to blocking synchronous collective communication with barriers. In contrast, FlashMoE fundamentally eliminates these inefficiencies with asynchronous, device-initiated data transfers overlapped with tiled computation all within a single kernel. FlashMoE further differentiates itself from SOTA works like COMET [12] and DeepEP [1], which also use this form of kernel-initiated communication but at a coarse-grained granularity and without complete kernel fusion.

10 Proof of Theorem 1↩︎

We begin with two necessary definitions vital to the proof.

We restate Theorem 1 and outline its proof below.

11 Memory Overhead↩︎

We measure the GPU memory required for the symmetric tensor \(L\) and runtime bookkeeping state of FlashMoE. The memory overhead primarily depends on the tile size, expert capacity (\(EC\)), and the number of experts (\(E\)). Table 3 summarizes the memory overhead across recent MoE models [50]–[55] during inference, showing that FlashMoE maintains a modest and predictable memory footprint. In particular, the symmetric tensor (\(ST\)) accounts for at most 2.15% additional memory relative to the total inference memory requirements.

5pt

12 Task Implementation↩︎

13 Actors↩︎

13.1 Processor↩︎

13.2 Scheduler↩︎

13.3 Subscriber↩︎

14 Implementation↩︎

15 FP16 Memory Throughput↩︎

References↩︎

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1. Correspondence to osayamen@stanford.edu↩︎