1 Introduction↩︎

The increasing complexity and computational demands of Deep Neural Networks (DNNs) have highlighted the limitations of traditional von Neumann architectures, particularly the memory wall bottlenecks in data movement between processing and memory units. To address this, Analog In-Memory Computing (IMC) crossbar architectures have emerged as a promising solution, offering the ability to perform computations directly within memory arrays, thereby significantly reducing data movement and energy consumption [1]. These architectures leverage the physical properties of resistive devices to store DNN weight parameters and perform matrix operations in the analog domain, enabling massive parallelization of DNN computations [2]. However, designing analog IMC systems presents unique challenges such as deep expertise in analog circuit design, an understanding of device physics, and careful consideration of various non-idealities such as parasitic effects, device variations, and noise [3].

Traditional analog IMC design approaches [1], [4] rely on manual optimization and iterative refinement, making it difficult to explore the vast design space of possible implementations as shown in Table 1. Furthermore, the lack of standardized tools and methodologies for IMC design has hindered rapid prototyping and evaluation of novel architectures. Recently, Large Language Models (LLMs) have shown success in digital design automation and hardware code generation [5]–[7]. The capability of LLMs in generating von Neumann architecture-based Artificial Intelligence (AI) accelerators has been recently explored [8], [9]. Nevertheless, their potential to generate promising non-von Neumann architectures, such as resistive IMC crossbar systems that allow for parallel and efficient vector-matrix multiplication, has remained unexplored. This gap stems from the knowledge intensive hardware design process and the scarcity of high-quality datasets and circuit catalogs due to proprietary data [6], [8].

\(^*\) Power-Area-Accuracy optimization.

This work introduces the first LLM-driven automated design exploration framework for IMC crossbar architectures dubbed LIMCA to generate design under user defined Power, Area, and Accuracy (PAA) constraints as highlighted in Table 1. The inherent challenges of IMC design including the need for precise circuit specifications, the consideration of complex analog behaviors, and the trade-offs among multiple competing objectives present both unique opportunities and challenges for LLM-based automation. Therefore, the core questions we seek to answer are the following– (RQ-1) Can we automate IMC design to address the growing shortage of specialized hardware in the semiconductor industry? (RQ-2) How can we deploy LLMs without cost-intensive fine-tuning? and can we effectively perform and evaluate Design Space Exploration (DSE)? (RQ-3) Can the major time consuming validation pipeline be fully automated? To answer these questions, this work presents the following contributions. (1) A DSE framework, LIMCA with Automatic Design Generation that leverages LLMs to map domain knowledge and introduces a fine-tuning-free approach for generating user-constrained designs from the space and generating the design of their choice. (2) LIMCA implements an automated validation strategy, eliminating human intervention, a No-Human-In-Loop (NHIL) approach ensuring efficient and scalable design evaluation. (3) An extensive open-source IMC dataset containing detailed variations of designs, along with PAA metrics for analog IMC.

Beyond these contributions, LIMCA provides four unique capabilities that distinguish it from existing tools: \((i)\) Natural Language DSE Interface users specify constraints in plain English rather than explicit parameter values; \((ii)\) Autonomous Design Navigation unlike lookup-based approaches, LIMCA proposes design solutions for configurations not in the dataset by learning patterns from existing data points through In-Context Learning (ICL), then autonomously refining toward valid solutions via NHIL; \((iii)\) Constraint Relaxation Negotiation when user constraints cannot be satisfied, LIMCA proposes alternative configurations with explicit trade-off explanations; and \((iv)\) Self-Correcting Pipeline hold-out validation experiments demonstrate that LIMCA proposes solutions for 100% of queries on unseen configurations.

2 Background, Challenges, and Motivations↩︎

LLM-Driven Hardware Design. LLMs have shown strong potential in automating Hardware Description Language (HDL) and High-Level Synthesis (HLS) code generation. Early works such as VeriGen [7] and ChatEDA [13] improve RTL-to-GDSII flows. ChipGPT [5] and Autochip [14] integrate LLMs for design generation and optimization, with Autochip refining Verilog through feedback. Dataset-driven frameworks have further advanced this direction. SA-DS [9] introduced an HLS dataset for DNN accelerators. Interactive approaches, such as Chip-Chat [15], extend LLM applicability to DSE. Meanwhile, RTLLM [16], GPT4AIGChip [8], and VerilogReader [17] highlight efficiency improvements in design and coverage-driven code analysis. Domain-specific accelerator generation is addressed by only a few efforts. GPT4AIGChip [8] targets HLS flows. On the analog domain, AnalogCoder [18], AnalogCoder-pro [19], SPICEPilot [6], and Masala-CHAI [20] pioneer SPICE-level netlist generation through ICL and agentic frameworks. Despite these advances, challenges remain. Most frameworks lack optimized prompting, tailored datasets, and model fine-tuning, while hallucination remains a persistent issue [9], [13]. Addressing these limitations is key to fully realizing LLMs’ potential in hardware and circuit design automation.

Analog IMC Crossbar and Simulation Frameworks. The resistive crossbar array (Fig. 1) forms the core computational primitive in IMC-based DNN accelerators, as it enables efficient parallel matrix-vector multiplications. In this architecture, DNN weights are encoded as the conductance of resistive cells, while activations are applied as voltages via DACs. Positive and negative weights are stored in separate arrays producing differential currents at the ADCs. The resulting MAC operation is expressed through \(G_{i,j}^{\pm}\), denoting the conductance of cells in the arrays. Existing IMC simulation frameworks can be grouped into two categories (Table 1). \((i)\) System-level simulators, such as NeuroSim [1], DNN+NeuroSim V2.0 [21], and MNSIM [2], use behavioral models to estimate area, power, and latency. MNSIM reports about 5% deviation from SPICE in energy and latency for a two-layer network, while NeuroSim integrates with ML simulators to evaluate training and inference accuracy across memory types [1]. However, these tools lack analog non-ideality modeling and circuit-level fidelity. Similarly, IBM’s AIHWKIT [4], though offering a PyTorch-based interface for crossbar simulation, inherits these limitations. \((ii)\) Circuit-level simulators, such as DPE [12], CCCS [10], and IMAC-Sim [11], provide higher accuracy by explicitly modeling device and circuit effects. DPE explores optimized weight mapping under non-idealities, while IMAC-Sim delivers a Python-based environment that generates SPICE netlists, incorporates parasitic interconnects, and supports partitioning, variability, and noise modeling. It enables both analog and digital emulation, with metrics such as power and accuracy extracted directly from HSPICE [11].

Despite progress in SPICE code generation [6], [18], IMC circuits pose unique challenges: even small networks require thousands of lines of repetitive SPICE code, and token limits restrict domain knowledge embedding. We address this by adopting IMAC-Sim’s Python-based approach.

Why LLMs Over Formal Methods. While the IMC design space can be partially characterized by formal constraint satisfaction, two fundamental limitations motivate an LLM-based approach. First, scalability: the full configuration space yields \(|D_{\text{full}}| = 900{,}000\) configurations, requiring \(\approx\)​13.7 years of exhaustive HSPICE simulation, rendering formal enumeration intractable. Second, soft constraint interpretation: user-specified intents such as “edge deployment” or “best accuracy under high variability” are not formal predicates until semantically resolved. A formal solver requires constraints pre-specified in closed form; LIMCA infers design intent from natural language and maps it to valid parameter configurations autonomously. Critically, where formal and lookup-based methods exhibit a hard failure mode, returning null for unseen configurations. LIMCA’s failure mode is soft: it proposes a candidate solution that is subject to iterative NHIL refinement, thereby providing a tractable starting point.

3 LIMCA - The Proposed Framework↩︎

LIMCA enables the automated design of analog IMC crossbars by leveraging LLMs to streamline design selection, generation, and verification, ensuring efficiency and adaptability in hardware-constrained environments. As illustrated in Fig. 2, the framework enables both user-guided and autonomous design instantiating by dynamically interpreting user-defined constraints and optimizing IMC architectures accordingly. The process begins with a user-specified prompt ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;), defining key design requirements such as performance metrics, hardware constraints, and optimization goals. The LLM extracts relevant parameters and formulates a weighted query ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;), determining whether an existing design from the design repository satisfies the given constraints. If an appropriate design is available, the system ranks and selects the optimal configuration ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;), presenting it to the user ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;). If no suitable design exists or if the user requests a new configuration, the framework triggers the Design Generation process ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;). The LLM selects and instantiates a novel IMC design configuration that aligns with the specified constraints, generating a corresponding Python-based design representation. The generated design undergoes an Automated Verification phase ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;), where a script-driven NHIL validation assesses its correctness. If the design meets the required specifications ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;), it is integrated into the design space repository ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;), ensuring continuous expansion of the available solution space. In cases where verification fails, diagnostic feedback is generated, pinpointing errors and guiding the LLM in refining subsequent iterations, thereby reducing hallucinations and redundant modifications ((X) [draw, scale=0.75, shape=circle, inner sep=0, fill=black, text=white, minimum size=0em]

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;). Unlike traditional design methodologies that rely on predefined architectures or manual fine-tuning, LIMCA dynamically adapts to evolving constraints, autonomously optimizing IMC designs while minimizing human intervention. This iterative and adaptive approach significantly enhances design efficiency, supporting various configurations and enabling scalable, high-performance IMC solutions. LIMCA is LLM-agnostic and can run with models available on Hugging Face [22].

IMC-Dataset. For LIMCA to achieve user-constrained outputs, we construct a dedicated dataset, the IMC-Dataset, to support the LLM. This dataset serves as a crucial component for integrating hardware-aware constraints into LLMs through either inference or fine-tuning. The dataset is built on IMAC-SIM [11], which facilitates both full analog circuit simulation and digital component emulation. It operates on the HSPICE Compiler, ensuring the generation of precise values as outlined in Table 1. To systematically explore the design space, we developed an automated framework to sweep key hardware parameters, capturing diverse configurations of IMC architectures. These parameters as shown in Fig. 3 includes different non-volatile memory devices (MRAM, RRAM, PCM, CBRAM), bit-cell configurations (1T-1R, 2T-1R, 1TG-1R), technology nodes, and bit-resolution(s). The dataset is primarily categorized based on crossbar size, with three distinct (\(n \times m\)) sizes. For each crossbar configuration, the following variations are considered: \(3 \times 4 \times 3 \times 6=216\), resulting in \(3 \times 216 = 648\) unique IMC instances across all three crossbar sizes. To extend the applicability of IMAC-SIM, we incorporate both digital and analog IMC variations. While the framework was initially designed for full analog simulations, we introduce an additional 216 analog data points by excluding the bit-resolution parameter, given the computational complexity of obtaining precise HSPICE simulation metrics across different bit-resolution(s). This ensures a broader exploration space while maintaining computational efficiency.

To the best of our knowledge, this is the first open-source IMC dataset with 400+ analog and digital variants. The dataset fixes the MLP configuration (\(400 \times 120 \times 84 \times 10\)) and \(20 \times 20\) input dimensions for computational feasibility, though the design-generation pipeline adapts to different user requirements. Planned expansions include additional MLP architectures and classification tasks. Because the combination of input feature-map size and MLP architecture exponentially increases the space (and compute), this release focuses on hardware exploration and avoids the high-dimensional complexity of varying network topologies across datasets. During creation, we fix the MLP configuration (\(400 \times 120 \times 84 \times 10\)), the dataset, and the number of MNIST training images [23], ensuring consistent evaluation and computational feasibility. The design-generation and automated-validation pipeline itself is not restricted to these settings and can adapt to user requirements. Dataset metrics are strongly influenced by input image dimensions; here they are \(20 \times 20\), given the specified MLP topology.

LLM Adaptation and Error Mitigation. Our fine-tuning-free approach intentionally demonstrates that effective IMC design automation is achievable with off-the-shelf LLMs, reducing the barrier to adoption and enabling rapid deployment without expensive model customization. This aligns with recent findings that in-context learning can match fine-tuned performance on domain-specific tasks when provided with well-structured exemplars [24]. Our LLM adaptation strategy employs: \((i)\) Structured Prompting—we decompose the design task into modular sub-tasks (parameter extraction \(\rightarrow\) constraint interpretation \(\rightarrow\) code generation \(\rightarrow\) verification), reducing cognitive load and error propagation at each step; \((ii)\) In-Context Learning—we provide the LLM with exemplar (X, Y) pairs from the dataset sorted by relevance to the query using k-nearest neighbor retrieval [25], enabling pattern recognition without gradient updates; \((iii)\) NHIL Error Correction—our pipeline automatically validates generated code against syntax correctness, parameter range validity, and constraint satisfaction, with failed generations triggering diagnostic feedback specifying error type and location; The effectiveness of NHIL correction is directly quantified by the Pass@1 versus Pass@3 performance gap reported in Tables 2 and 3: Pass@1 reflects single-shot generation without correction, while Pass@3 captures iterative NHIL refinement. The consistent convergence to 100% Pass@3 across all models demonstrates that the feedback loop deterministically resolves the dominant failure categories, syntax errors (38%) and parameter range violations (31%), which together constitute 69% of all generation failures, eliminating the need for human intervention in error diagnosis and correction.and \((iv)\) Hallucination Mitigation—by constraining the LLM to generate Python code calling IMAC-Sim APIs rather than raw SPICE netlists, we bound the output space to valid configurations, preventing hallucination of non-existent device types or invalid parameter combinations.

4 Experimental Analysis↩︎

Design Space Exploration. The queries driving the DSE are generated by ChatGPT-4o [26]. A total of 30 queries are systematically divided based on specific objectives: 10 queries prioritize power efficiency with relaxed technology node constraints, 10 emphasize area optimization, and 10 enforce hard constraints on design feasibility. The selection schema of the DSE for IMC accelerators, inferring from the dataset by LIMCA, is summarized in Table [exp]. From Table [exp], we observe area reduction with increasing crossbar size due to improved partitioning that reduces switch-box overhead (Fig. 4). Considering edge vision sensor requirements, a nominal power limit of \(\leq\)​3W is imposed while targeting accuracy \(\geq\)​96%. Entries in green satisfy these constraints; yellow highlights near-optimal configurations (e.g., 64\(\times\)​64 crossbar with 1T1R-PCM at 7nm or 9nm). Table 2 summarizes LIMCA’s DSE performance across multiple LLMs. All achieve 10/10 Pass@3 across constraint categories, indicating reliable design selection within 3 attempts. Pass@1 varies: Qwen2.5-Coder-32B-Instruct leads with \(\geq\)​9/10 across categories, while Mamba-Codestral-7B-v0.1 shows consistent 8/10 performance.

Baseline Comparison. We evaluate LIMCA against three DSE baselines: exhaustive Grid Search, Genetic Algorithm (GA), and a Rule-Based system. The GA employs a population of 50, tournament selection (\(k=3\)), single-point crossover (0.8), bit-flip mutation (0.1), and terminates at 100 generations or upon 5-generation stagnation. Soft constraints (e.g., "edge deployment" \(\rightarrow\) power \(<\) 3W) are managed via a weighted fitness function with quadratic penalties. Under an equivalent budget of \(\sim\)​500 evaluations, Grid Search and GA are limited to existing database configurations, failing on extrapolation queries (0% success) and struggling with soft constraints (45% and 62%, respectively). In contrast, LIMCA leverages natural language understanding to achieve 93% on soft constraints and 100% on extrapolation, autonomously generating novel, valid designs where traditional methods return "not found."

\(^\dagger\)Percentage of queries receiving a proposed solution. Traditional methods return “not found” for configurations outside the database.

Design Creation. LIMCA synthesizes IMC designs with automated validation. Design requests originate from ChatGPT queries and are executed by LIMCA, which verifies each result against specified constraints. Table 4 reports Pass@1 and Pass@3 for design generation and verification. For generation, LIMCA attains \(\geq\)​89% Pass@1 and 100% Pass@3, indicating reliable synthesis. For verification, we inject erroneous designs to stress-test the framework; LIMCA detects and corrects errors with 91.5% average Pass@1 and 100% Pass@3, demonstrating robust NHIL-based error recovery. Failure analysis of 500 generation attempts reveals four primary modes: syntax errors (38%), parameter range violations (31%), device type hallucinations (18%), and constraint mismatches (13%), with the first two categories (69%) being deterministically correctable given NHIL diagnostic feedback.

Simulation Methodology. Power and area metrics are derived from HSPICE simulation of the complete crossbar netlist. Inference accuracy is computed via behavioral simulation using SPICE-characterized device models applied to a representative subset of test images—not a full transistor-level simulation of 10,000 images, which would be computationally infeasible. This approach provides SPICE-level fidelity for circuit metrics while enabling practical accuracy evaluation.

Scalability Analysis. The IMC design space is characterized by the configuration vector \(\mathbf{X}\) = (, , , , , , ). While our current dataset fixes the MLP topology and pixel dimensions for computational feasibility, the full design space is combinatorially large. With realistic parameter ranges \(|X_{\text{crossbar}}| = 6\) sizes (16\(\times\)​16 through 256\(\times\)​256), \(|X_{\text{tech}}| = 6\) nodes (7nm–45nm), \(|X_{\text{bitcell}}| = 4\) configurations, \(|X_{\text{device}}| = 5\) types, \(|X_{\text{MLP}}| \geq 50\) topologies, \(|X_{\text{pixel}}| = 5\) dimensions, \(|X_{\text{dataset}}| = 5\) benchmarks—the full design space yields \(|D_{\text{full}}| = 900{,}000\) configurations. At approximately 8 minutes per HSPICE simulation, exhaustive enumeration would require \(\approx\)​13.7 years of continuous computation. This intractability motivates LIMCA’s approach: rather than enumerating all configurations, the LLM learns to navigate the design space intelligently, proposing valid solutions for queries and self-correcting through NHIL feedback.

Generalization Validation. To demonstrate that LIMCA generalizes beyond memorization, we conducted hold-out experiments removing entire configuration categories (e.g., all 64\(\times\)​64 crossbars, all PCM devices) from the LLM’s context. Unlike Grid Search, which returns “not found” for any configuration outside its database, LIMCA proposes solutions for 100% of such queries. While extrapolation to fundamentally different device physics remains challenging (e.g., PCM’s 0.5W power profile versus RRAM’s 3–8W), LIMCA demonstrates genuine pattern recognition for interpolation within the known design space, autonomously navigating toward constraint-satisfying configs via iterative NHIL refinement.

Trade-off Reasoning. Beyond selection, LIMCA articulates device trade-offs. For the query “best accuracy under high variability,” LIMCA responds: “PCM achieves 98–100% accuracy across crossbar sizes due to tighter conductance distribution, while RRAM accuracy drops from 100% at 16\(\times\)​16 to 18% at 64\(\times\)​64. Recommendation: PCM with 1T1R at 7nm (0.46W, 100% accuracy).” This demonstrates the LLM learning/ articulating relationships between device physics and performance.

Design Exploration Cost. To assess DSE time under identical constraints (\(\leq\)​3W power, \(\geq\)​96% accuracy), a circuit expert conducted manual optimization using CCSS [10] and IMAC-Sim [11]. Each iteration required debugging, reconfiguration, and reruns, with total optimization ranging from 140–398 minutes (CCSS) and 92–154 minutes (IMAC-Sim). LIMCA retrieves existing configurations in seconds or synthesizes new designs in under 8 minutes (Table 5), achieving 11.5\(\times\)–49.7\(\times\) speedup while eliminating manual intervention.

5 Conclusion↩︎

In conclusion, this work introduces LIMCA, a novel open-sourced framework that leverages LLMs to automate the design and evaluation of IMC crossbar architectures with no human intervention in design synthesis and SPICE-level verification. By systematically generating and validating SPICE-characterized configurations, LIMCA accelerates design exploration while satisfying key power, area, and accuracy constraints. Baseline comparisons demonstrate significant advantages over grid search and rule-based approaches.

6 Acknowledgments↩︎

The authors used Claude Sonnet only to improve writing clarity and readability, while all scientific content, including ideas, experiments, and conclusions, was created entirely by the authors.

References↩︎

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1. This work is supported in part by Synopsys Research Gift and the National Science Foundation (NSF) under grant no. 2228028, 2409697, and 2504839.↩︎